Full citation: Ahmed, F., and Milor, L. (2016). “Online Measurement of Degradation Due to Bias Temperature Instability in SRAMs.” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24(6), 2184–2194. DOI: 10.1109/TVLSI.2015.2500900.
Plain-Language Overview
SRAM cells can gradually become less reliable as their transistors age. One important cause is bias temperature instability (BTI), which changes transistor threshold voltage over time. The cell may continue to read and write correctly for years while its safety margins steadily shrink, eventually producing a failure.
Conventional memory tests and ECC normally react after an error occurs. This paper asks a more useful reliability question: Can an SRAM identify cells that are becoming dangerously weak before they actually fail?
The authors propose an on-chip monitoring system that measures the electrical strength of individual SRAM transistors during special test modes. The technique separately monitors:
- NBTI degradation of the pMOS latch transistors
- PBTI degradation of the nMOS latch transistors
- BTI-related degradation of SRAM access and decoding paths
The measurement is converted into an oscillation frequency. As the relevant transistors age and become weaker, bitline charging or discharging slows, and the measured frequency decreases.
A major advantage is that the internal 6T SRAM cell itself does not need to be modified. The scheme manipulates existing memory-control signals and adds monitoring circuitry around the array. A fabricated 64-kB SRAM test chip verifies that the expected frequency degradation can be measured in silicon.
The broader goal is preventive repair: identify a weak cell while it still works and then replace or deactivate it using redundant SRAM resources before an actual memory error occurs.
What Problem the Paper Addresses
SRAM reliability is traditionally protected through a combination of design margin, ECC, redundancy, and periodic testing.
The problem is that these mechanisms have important limitations.
Conventional guard-bands are conservative
SRAM designers reserve margins for both:
- Manufacturing process variation
- Expected aging over the product lifetime
Large aging margins reduce opportunities to optimize voltage, performance, and area.
ECC normally acts after failure
ECC is valuable once a bit has become erroneous, but it does not normally tell the system that a currently functioning bit is approaching failure.
If a word already contains one correctable failed bit, another failure may exhaust the available correction capability.
Ordinary memory tests also detect failures after they appear
Pass/fail testing identifies a cell after one of its electrical specifications has already been violated. The paper instead seeks to detect the degradation leading toward that violation.
Array-level leakage is not a reliable per-cell health indicator
One existing BTI-monitoring approach measures quiescent array current, IDDQ. This can correlate with NBTI when BTI is the only degradation mechanism.
However, the Figure 1 plots on page 1 show a serious limitation. In the absence of gate-oxide breakdown, array leakage correlates well with threshold voltage. Once GOBD creates a low-resistance leakage path, that correlation becomes heavily corrupted. Aggregate leakage also cannot identify which particular SRAM cell is weak.
The paper therefore seeks a cell-specific monitor whose result can be connected directly to the performance margins that determine SRAM failure.
Questions the Paper Answers
The study addresses questions including:
- Which SRAM performance margins deteriorate most strongly under NBTI?
- Which margins deteriorate most strongly under PBTI?
- Can pMOS and nMOS aging be measured separately within a conventional 6T cell?
- Can the measurement identify a weak cell before a functional error occurs?
- How can pMOS strength be measured when conventional SRAM read operations mainly exercise nMOS devices?
- Can ordinary read current be used to monitor PBTI?
- Can the same monitoring concept detect aging of memory decoder and access paths?
- Can the technique operate without adding transistors inside every SRAM bitcell?
- Does the proposed monitor produce measurable degradation on fabricated silicon?
- What area and power overhead does the monitoring hardware introduce?
- Can predictive monitoring be combined with ECC and memory redundancy to improve long-term reliability?
Key Technical Terms and Definitions
Bias Temperature Instability
Bias temperature instability (BTI) is a time-dependent degradation process that alters transistor electrical characteristics, particularly threshold voltage.
The paper considers both NBTI and PBTI.
Negative Bias Temperature Instability
NBTI primarily affects pMOS transistors under negative gate-to-source voltage stress.
As the pMOS devices weaken, SRAM read stability can decrease.
Positive Bias Temperature Instability
PBTI affects nMOS devices under positive gate stress.
In a 6T SRAM cell, weakening of the latch nMOS devices can affect both read stability and read-access speed.
Reaction–Diffusion Model
The paper uses a reaction–diffusion (R–D) BTI model as its main degradation reference because suitable experimental data were widely available.
The authors also discuss random-telegraph-noise-based descriptions but use R–D modeling for the presented simulations.
BTI Recovery
BTI is partly recoverable when electrical stress is removed.
This is important in SRAM because the two complementary sides of the cell do not necessarily experience identical stress. When one device is strongly stressed, its counterpart may be recovering.
Cells that remain in the same state for long periods can therefore age more severely than cells whose data changes frequently.
The paper notes prior observations of lifetime differences of up to approximately 4× between dc- and ac-stressed devices.
Process Variation
Small SRAM transistors are highly susceptible to manufacturing variation.
The paper models initial transistor threshold voltage statistically and combines that variation with a random component of BTI degradation.
Thus, two nominally identical cells can:
- Begin with different strengths
- Accumulate different amounts of degradation
Static Noise Margin
Static noise margin (SNM) describes the amount of dc disturbance an SRAM cell can tolerate without flipping state.
The paper considers both read and retention SNM.
Read SNM
Read SNM measures cell stability while the access transistors are active during a read.
For the studied design, this becomes the most important metric for NBTI-induced cell failure.
Write Margin
Write margin indicates how easily the cell can be forced into the opposite state during a write.
Interestingly, weakening the pMOS devices through NBTI can slightly improve writability because the pull-up device resisting the write becomes weaker.
Access Time
Access time is the delay required to perform the SRAM read operation.
The study finds that access time is relatively insensitive to NBTI of the pMOS cell devices but is affected by PBTI in the nMOS devices and by BTI in memory peripheral logic.
Minimum Operating Voltage
VDD-min is the minimum supply voltage at which the SRAM satisfies its required probability of successful operation.
It depends on:
- Read stability
- Write margin
- Access time
- Process variation
- Aging
As BTI worsens critical margins, the voltage necessary to maintain the same SRAM yield can increase.
Probability of Cell Failure
The paper calculates P_fail statistically from distributions of SRAM performance margins.
A desired SRAM yield and memory size imply an allowable single-cell failure probability. The minimum operating voltage is then chosen so that cell failure probability remains below this requirement.
Weak Cell
A weak cell still operates correctly but lies sufficiently close to a performance limit that continued BTI degradation is likely to cause future failure.
Detecting these cells is the central objective of the proposed monitoring system.
Design for Testability
The added DFT circuitry places cells and memory paths into special test configurations without modifying the compact SRAM-cell layout itself.
Data-Path Ring Oscillator
The DPRO concept converts an existing logic path into an oscillator during test mode.
Its frequency represents the total path delay:
more aging → longer delay → lower oscillation frequency.
The paper applies this idea to memory decoding and access paths.
Workflow
1. Model statistical transistor aging
The analysis begins with a conventional 6T SRAM cell.
Threshold voltage includes:
- Initial process variation
- Mean BTI degradation
- Random device-to-device variation in degradation
The two complementary latch devices receive complementary duty cycles because one side is stressed while the other is recovering.
2. Calculate SRAM performance distributions
Monte Carlo simulations calculate statistical distributions for:
- Read SNM
- Retention SNM
- Write margin
- Access time
The analysis is conducted as a function of supply voltage and aging time.
3. Convert cell-level specifications into failure probability
For each performance metric, the calculated mean and variation are compared with the required specification.
This produces a probability that a random SRAM cell violates that performance criterion.
4. Determine NBTI’s dominant failure indicator
The plots on page 4 show that increasing NBTI has a strong effect on read SNM.
In comparison:
- Write margin slightly improves.
- Access time remains nearly unchanged for pMOS-cell NBTI.
Consequently, read SNM becomes the primary cell-level health indicator for NBTI in the studied design.
5. Determine PBTI’s dominant indicators
PBTI affects the nMOS devices differently.
The simulations show that both:
- Read SNM
- Access time
degrade as PBTI progresses.
Write margin also degrades slightly but is less limiting in the studied conditions.
6. Connect performance margin to transistor threshold voltage
The authors derive relationships linking transistor threshold voltage to the SRAM metrics that ultimately determine failure.
For NBTI:V_tp→read SNM
For PBTI:V_tn→{read SNM & access time
This is important because the monitor does not need to measure SNM directly. It can instead measure a current related to transistor strength.
7. Create a special NBTI test state
Measuring pMOS strength during an ordinary SRAM operation is difficult.
During a normal read, bitline discharge mainly passes through the access and pull-down nMOS transistors. During a write, the interval where pMOS current dominates is short.
The authors therefore create a special NBTI test condition in which both bitlines are forced to ground.
As illustrated in Figure 9 on page 5, this puts both pMOS latch devices into a conducting condition so that their currents flow toward the bitlines.
8. Measure pMOS strength through bitline current
Simulation shows that the resulting test currents are:
- Strongly dependent on pMOS threshold voltage
- Relatively insensitive to nMOS-device variation
The current can therefore act as a pMOS aging indicator.
A threshold can be established such that:
test current → estimated pMOS strength → expected read SNM → weak/good cell classification.
9. Monitor PBTI using the read operation
PBTI monitoring is simpler.
Read current naturally depends on the pull-down nMOS devices.
The normal read configuration therefore serves as the PBTI test state.
A decreasing read-current measurement indicates increasing nMOS threshold voltage and can be related to the read-SNM and access-time limits.
10. Convert charging/discharging delay into frequency
Rather than requiring a precise analog current measurement externally, the proposed circuitry generates a repetitive test cycle.
Bitline charging or discharging causes a voltage-level sensor to toggle the relevant controls. The resulting loop oscillates.
Its frequency becomes the digital health indicator.
For example:
- Weak pMOS → slower bitline charging → lower NBTI-test frequency
- Weak nMOS → slower bitline discharge → lower PBTI-test frequency
11. Monitor memory peripheral logic
A memory can also fail because the decoder or access circuitry becomes too slow, even if the bitcell itself remains stable.
The paper therefore incorporates a data-path ring-oscillator concept.
Selected decoder paths are converted into oscillating paths during test mode.
Oscillation frequency directly represents path delay and therefore reveals approaching BTI-induced timing failure.
12. Measure complete access-path degradation
A separate access-time mode includes both:
- Wordline decoder delay
- Bitline discharge delay
The procedure operates similarly to the PBTI cell test, except the wordline is generated through the normal decoder path.
When the bitline drops below a selected level, the sensor disables the wordline and begins precharge, producing another oscillating loop.
Thus, degradation of the cell and decoding path is reflected in the same measured frequency.
13. Test every SRAM address
By cycling through addresses, the monitor can examine the SRAM array for abnormal or near-failure cells.
The proposed design tests all columns for a selected word in parallel.
14. Preserve normal SRAM operation
The proposed scheme makes no changes to the internal SRAM-cell structure.
Monitoring circuitry resides in the memory periphery, which protects the density and normal performance of the array.
15. Validate the technique in silicon
The authors fabricate a test chip using IBM 130-nm CMOS technology.
Its SRAM macro contains:
- 64 kB
- 8k words
- Four-way column multiplexing
The chip is stressed at:
- 90 °C
- 1.5× nominal supply voltage
Measurements are collected every few hours during approximately 24 hours of accelerated stress.
16. Use frequency degradation as the experimental observable
The fabricated monitor converts bitline charge/discharge delay to an on-chip frequency.
With increasing aging:
- NBTI-test frequency declines.
- PBTI-test frequency declines.
- Access-time-test frequency declines.
The measured trends agree qualitatively with the operating principle predicted by the simulations.
17. Reconfigure before failure
Once a cell’s monitor approaches the threshold corresponding to unacceptable SNM or access time, that cell can be removed from active use.
Possible responses discussed by the paper include:
- Replacing it with redundant cells
- Remapping addresses
- Combining the monitor with ECC so that a second failure can be prevented before ECC capability is exceeded
Main Findings
NBTI primarily threatens read stability in the studied SRAM
The simulation results show that NBTI degradation of the pMOS latch transistors has a strong effect on read SNM.
As aging progresses, the minimum voltage necessary to satisfy the read-stability requirement rises.
By comparison:
- Write margin slightly improves.
- Access time is nearly unaffected by bitcell pMOS NBTI.
The page 4 graphs make this separation particularly clear.
PBTI affects both stability and speed
PBTI degradation of the nMOS latch devices affects both:
- Read SNM
- Access time
Therefore, a PBTI health monitor must consider the more restrictive of those two limits rather than relying on stability alone.
pMOS and nMOS degradation must be separated
A conventional pass/fail SRAM test cannot reveal whether deteriorating margin originates from the pMOS or nMOS side of the cell.
The paper’s test states intentionally decouple them:
- Special both-bitlines-low condition → pMOS/NBTI
- Read current → nMOS/PBTI
This provides more diagnostic information than simply measuring VDD-min.
A working cell can be classified as risky before it fails
Because test current and frequency are continuously related to transistor strength, the monitor does not need to wait for a bit error.
The threshold can be placed ahead of the functional-failure point.
This is the paper’s key difference from conventional BIST or ECC: prediction rather than detection after failure.
Whole-array IDDQ monitoring is vulnerable to unrelated leakage mechanisms
Figure 1 demonstrates that aggregate leakage can serve as a useful NBTI indicator only while no large competing leakage source is present.
Gate-oxide breakdown can dominate array leakage and destroy the relationship between total leakage and BTI-induced threshold-voltage change.
The proposed per-cell test avoids relying solely on one global leakage value.
Logic-path aging matters in addition to bitcell aging
A cell may remain electrically stable while memory access fails because:
- The decoder becomes too slow.
- Wordline activation is delayed.
- Peripheral circuitry accumulates BTI.
The DPRO-based monitoring therefore extends the concept beyond the 6T cell itself.
Silicon measurements demonstrate the expected aging signature
The experimental Figure 20 on page 9 shows measured frequency distributions for several monitoring modes.
As accelerated BTI stress progresses, frequencies shift downward.
The authors explain that process variation dominates much of the initial frequency spread, while accumulated BTI contributes increasingly to the distribution as stress continues.
The failing tail of the distribution is more important than the mean
The authors emphasize that the first cells to fail are not average cells.
They lie in the extreme tail of the process-and-aging distribution and therefore exhibit monitor frequencies substantially below the population mean.
The measured cell data were approximately normally distributed, and the authors report no evidence of a fundamentally different trend in the tails.
The internal SRAM array remains unchanged
A significant practical result is that no transistor is added to every 6T cell.
The extra components consist mainly of:
- Bitline voltage-level sensors
- Multiplexing/control circuitry
- A digitizer/delay-chain structure
This preserves SRAM density.
Estimated area overhead is small
For an assumed 64-bit-I/O memory with 70% array efficiency, the paper estimates monitoring overhead of approximately:
- 0.08% for a 512-kb SRAM
- 0.04% for a 1-Mb SRAM
The percentage falls as memory capacity increases because much of the digitizing circuitry does not scale with the number of stored bits.
Test power is expected to be negligible over product lifetime
A monitoring event consumes power comparable to only a small number of ordinary memory operations.
Because BTI evolves over years, the authors argue that the test need only run a few times per year at most.
The DFT block can also be power-gated during normal operation.
Technical Significance
The paper’s principal technical contribution is the transition from BTI estimation to BTI-based failure prediction.
Rather than simply estimating an average threshold-voltage shift, the method establishes a chain:
- BTI changes transistor threshold voltage.
- Threshold voltage changes transistor drive current.
- Test current changes bitline charge/discharge delay.
- Delay changes oscillation frequency.
- Frequency can be related to SRAM performance specifications.
- A cell can therefore be flagged before crossing the functional-failure boundary.
A second important contribution is the separation of NBTI and PBTI monitoring through carefully engineered test states.
The approach avoids trying to infer both mechanisms from one ambiguous SRAM pass/fail result.
A third contribution is the inclusion of memory peripheral timing. The monitor recognizes that SRAM reliability includes both:
- Bitcell stability
- Access-path timing
The DPRO-based mode provides a way to monitor decoder degradation directly.
Finally, the design achieves this without modifying every memory bitcell, which is important because even a small per-cell overhead would become expensive across large SRAM arrays.
Industrial Impact
Source-supported implication: The proposed monitoring system could allow an SRAM to detect cells approaching BTI-induced failure and reconfigure around them before they generate field errors.
Potential applications include:
- Processor cache reliability
- Automotive SRAM
- Aerospace and defense electronics
- Long-lifetime embedded systems
- Safety-critical controllers
- High-availability computing
- Aging-aware memory redundancy
- Post-silicon reliability management
The method can complement ECC rather than replace it.
ECC can tolerate a first bit failure, while predictive monitoring can determine whether another cell is becoming sufficiently weak that reconfiguration should occur before a second error appears.
Interpretation: A practical system could use monitor frequency as a health indicator in firmware. The threshold for retirement might be chosen according to the product’s safety target: a safety-critical controller could replace cells earlier, while a consumer device could accept a smaller margin to preserve capacity.
The same principle could also help reduce unnecessarily conservative lifetime guard-bands because the actual fabricated memory is monitored instead of assuming every part follows the worst possible aging trajectory.
Why the Paper Matters
Most conventional reliability techniques answer the question:
“Has this bit failed?”
This paper instead tries to answer:
“Which bit is likely to fail next?”
That difference is significant.
Waiting for a failure works reasonably well when ECC has enough spare correction capability. But in extremely large memories or high-reliability products, preventing the error can be preferable to correcting it afterward.
The paper also recognizes that an SRAM failure is not represented by one universal aging metric. NBTI and PBTI affect different transistors and different circuit margins. Monitoring them separately produces a more physically meaningful indication of how close a cell is to failure.
Finally, the low estimated area overhead and lack of bitcell modification make predictive health monitoring substantially more practical than schemes requiring additional circuitry in every memory cell.
Limitations and Scope
The results should be interpreted within several important boundaries:
- The detailed statistical simulations use a conventional 6T SRAM cell and process statistics associated with the technologies available to the authors.
- The silicon demonstrator uses IBM 130-nm CMOS, which is much older than current advanced-node SRAM technologies.
- The experimental stress uses 90 °C and 1.5× nominal supply voltage for roughly 24 hours. It verifies the monitoring trend under accelerated conditions rather than directly demonstrating many years of normal-field aging.
- The paper assumes BTI is the dominant degradation mechanism under the selected accelerated stress conditions.
- Other wearout mechanisms are not comprehensively diagnosed by the proposed monitor.
- Gate-oxide breakdown is discussed primarily as a failure mode that can corrupt aggregate IDDQ-based BTI measurements rather than as a mechanism simultaneously estimated by this monitor.
- The statistical aging analysis uses the reaction–diffusion BTI formulation as its reference model. Different BTI physics or calibration parameters would alter predicted threshold shifts.
- Initial threshold-voltage variation and BTI variation are treated as uncorrelated in the presented statistical formulation.
- The SRAM state probabilities used in simulations are generated from an assumed distribution rather than from one specific application workload.
- Actual BTI degradation depends on the cell’s long-term stored-data history and recovery periods.
- The NBTI test mode is destructive to the stored data. The paper notes that temporary storage can preserve the bits being tested, or the procedure can be run during startup when data preservation is unnecessary.
- The added voltage-level sensing and digitizer circuitry still requires design, calibration, and verification for a particular SRAM implementation.
- Process variation produces substantial initial frequency spread, so weak-cell thresholds must distinguish aging from manufacturing differences.
- The sense-amplifier-to-output portion of the access path is discussed as compatible with the approach but was not included in the fabricated test-chip implementation.
- The area figures of 0.08% and 0.04% are estimates based on stated assumptions about I/O width, array efficiency, sensor size, and digitizer size rather than universal overhead values.
- Successful failure avoidance ultimately requires sufficient redundant memory or another reconfiguration mechanism.
- Predicting a future error requires choosing a warning threshold ahead of the actual failure limit; the optimum margin depends on the product’s desired reliability and false-retirement tolerance.
- The work demonstrates monitoring feasibility but does not report a large fleet-scale field deployment validating long-term prediction accuracy.
Concise Technical Abstract
This paper proposes an on-chip methodology for predicting bias-temperature-instability-induced failures in conventional 6T SRAM before functional errors occur. Statistical transistor models combine process variation with time-dependent NBTI and PBTI threshold-voltage degradation, and Monte Carlo simulations relate aging to read static noise margin, write margin, access time, minimum operating voltage, and cell failure probability. NBTI primarily degrades read stability in the studied cell while slightly improving write margin and producing little direct change in access time; PBTI degrades both read stability and access time. To monitor these mechanisms separately, the authors introduce a special NBTI test state in which both bitlines are forced low, making measured bitline currents strongly dependent on pMOS strength, while conventional read-current behavior is used to sense nMOS PBTI. Bitline charging and discharging delays are converted into oscillator frequency, enabling digital readout of individual-cell degradation. A data-path ring-oscillator technique extends monitoring to decoder and memory-access logic. The approach requires no modification to the internal SRAM bitcell and is experimentally validated using a 64-kB IBM 130-nm SRAM stressed at 90 °C and 1.5× nominal supply voltage, where NBTI, PBTI, and access-test frequencies decrease with accumulated stress. Estimated monitor area overhead is approximately 0.08% for a 512-kb memory and 0.04% for a 1-Mb memory. By detecting weak cells before specification failure, the method enables redundancy or address reconfiguration to support proactive SRAM reliability management.
Linda Milor 
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