Impact of Linewidth on Backend Dielectric TDDB and Incorporation of the Linewidth Effect in Full Chip Lifetime Analysis

Full citation: Bashir, M. M., & Milor, L. (2015). “Impact of Linewidth on Backend Dielectric TDDB and Incorporation of the Linewidth Effect in Full Chip Lifetime Analysis.” IEEE Transactions on Semiconductor Manufacturing, 28(1), 25–34. https://doi.org/10.1109/TSM.2014.2383832. 

Plain-Language Overview

This paper investigates why the reliability of the insulating material between copper interconnects can change when the metal linewidth changes, even when the designed spacing between neighboring metal lines stays the same.

Conventional backend dielectric reliability models largely assume that time-dependent dielectric breakdown (TDDB) is determined by the electric field across the dielectric, which in turn depends mainly on line-to-line spacing. Bashir and Milor show that this assumption is incomplete for the 45 nm technology they studied.

Their experiments indicate that narrower and wider metal lines are manufactured differently from their drawn dimensions. These changes alter the actual physical spacing between neighboring lines. The authors trace much of this behavior to aspect-ratio-dependent etching, particularly lateral etching. Narrow lines can undergo more lateral etching, reducing the dielectric spacing and therefore shortening TDDB lifetime.

The paper then incorporates this linewidth dependence into a methodology for estimating full-chip dielectric lifetime, rather than relying only on nominal line spacing.

A central practical finding is that simply making wires wider does not automatically produce a large chip-level reliability improvement. Wider lines may improve local dielectric lifetime, but routing changes can increase the vulnerable dielectric area and offset much of the benefit.

What Problem the Paper Addresses

Backend interconnect reliability models commonly divide a chip into dielectric segments and estimate lifetime using the spacing and vulnerable length of each segment.

Traditionally, the relevant layout parameters can be represented as:

• S: spacing between adjacent metal lines.
• L: length over which those lines run parallel and expose dielectric to electrical stress.

The problem identified by the authors is that two dielectric regions with the same nominal spacing may not have the same TDDB lifetime if the neighboring metal widths are different.

Earlier studies had observed a linewidth dependence, but linewidth and pattern density were changed simultaneously. Consequently, those experiments could not determine whether the lifetime change was caused by linewidth itself, pattern density, or the manufacturing effects associated with either variable.

This paper therefore separates linewidth from pattern density experimentally and asks what additional layout information must be included in full-chip TDDB analysis.

Questions the Paper Answers

The study addresses several connected questions:

1. Does backend dielectric TDDB depend on metal linewidth when nominal line spacing is held constant?
   The experimental results indicate that it does.
2. Is pattern density responsible for the observed linewidth-dependent lifetime difference?
   The authors’ specially designed structures indicate that pattern density is not the dominant cause in their experiments.
3. Can electric-field fringing explain the linewidth effect?
   Finite-element simulations suggest no unexpected field enhancement beyond what follows from the actual physical spacing.
4. Can line-edge roughness explain the difference between linewidths?
   Line-edge roughness reduces lifetime, but the modeled degradation is similar for the different linewidth structures and therefore does not explain the linewidth-dependent trend.
5. Are lithographic effects responsible?
   The observed geometry trends do not agree with the trends expected from the optical proximity effect or flare.
6. What manufacturing mechanism best explains the results?
   The evidence points toward aspect-ratio-dependent etching and lateral etching, which modify printed linewidth and therefore actual dielectric spacing.
7. How can the effect be incorporated into chip-level reliability prediction?
   The authors extend layout extraction so that each vulnerable dielectric segment is associated not only with length and spacing, but also with the widths of the adjacent metal lines.

Key Technical Terms and Definitions

Time-Dependent Dielectric Breakdown (TDDB)
A progressive reliability failure in which an insulating material eventually becomes conductive after prolonged electrical stress.

Low-k dielectric
An insulating material with a low dielectric constant used between metal interconnects to reduce capacitance and improve integrated-circuit performance.

Cu/low-k interconnect
An interconnect system combining copper wiring with low-k dielectric material.

Linewidth
The width of a metal interconnect line. The paper distinguishes between the drawn linewidth in the layout and the actual manufactured linewidth.

Linespace
The dielectric distance between adjacent metal lines. The authors distinguish between the drawn spacing $S_D$ and the actual manufactured spacing $S_A$.

Pattern density
The fraction of a region covered by interconnect material. Earlier work had confounded pattern density with linewidth.

Weibull distribution
A statistical distribution widely used for reliability and breakdown modeling. The paper uses two major Weibull parameters:

• η (eta): characteristic lifetime.
• β (beta): Weibull shape parameter describing the spread and failure-rate behavior.

Bimodal failure distribution
A distribution containing two distinct failure populations. The authors consider an early-failure mechanism and a bulk-dielectric failure mechanism.

Line Edge Roughness (LER)
Small random variations along the edges of patterned metal lines. These variations create local changes in dielectric spacing.

Aspect Ratio
The relationship between feature height and width. The experiments show an important relationship between aspect ratio, etch behavior, printed geometry, and TDDB lifetime.

Aspect-Ratio-Dependent Etching (ARDE)
A manufacturing effect in which etch behavior changes according to feature geometry and aspect ratio.

Lateral etching
Etching that occurs sideways into a feature rather than strictly vertically. The authors argue that increased lateral etching of narrow features can reduce the spacing between neighboring conductors.

Vulnerable length
The length over which two neighboring wires run in parallel and therefore expose the intervening dielectric to breakdown stress.

Area scaling
A reliability calculation that adjusts test-structure lifetime distributions to account for differences in vulnerable dielectric area.

Workflow

The paper follows a multi-stage experimental and modeling workflow.

1. Design Test Structures That Separate Linewidth and Density

The researchers fabricate comb structures in 45 nm copper/low-k technology.

The principal linewidth structures are:

• 1X: minimum linewidth.
• 3X: three times minimum linewidth.
• 5X: five times minimum linewidth.
• 1X/5X: a nonuniform structure containing both narrow and wide lines.

All structures use the same nominal line spacing.

Importantly, the 3X and 1X/5X structures have the same pattern density but different linewidth configurations. This provides a direct test of whether density or linewidth controls the lifetime variation.

2. Perform TDDB Stress Testing

The structures are subjected to constant electrical and thermal stress, and their time-to-failure distributions are measured.

The resulting Weibull plots for the 1X, 3X, and 5X structures show a substantial increase in characteristic lifetime with increasing linewidth.

Figure 4 on page 3 illustrates these distinct failure distributions.

3. Evaluate the Statistical Form of the Failures

The experimental data do not follow a simple single Weibull distribution.

The authors consider two explanations:

• Two physical failure populations, producing a bimodal Weibull distribution.
• Die-to-die process variation, producing a compound Weibull distribution.

Rather than claiming that one explanation is definitively correct, the subsequent modeling considers both interpretations.

4. Determine Whether Pattern Density Is Responsible

The authors compare the 3X structure with the 1X/5X structure.

Although they have equal pattern density, their failure distributions differ significantly.

Figure 5 on page 4 shows this comparison.

The result indicates that pattern density alone cannot account for the lifetime variation.

5. Measure Actual Manufactured Geometry

Scanning electron microscopy is used to determine how fabricated linewidth differs from the drawn design.

The measurements show that:

• Narrow lines tend to become wider than drawn.
• Wide lines tend to become narrower than drawn.

As Figure 6 on page 4 demonstrates, the manufactured linewidth error changes systematically with the intended linewidth.

Because the pitch remains constrained, a linewidth shift also changes the actual dielectric spacing:$$S_A=S_D-\mathrm{\Delta }W$$

Thus, the reliability-relevant spacing is not necessarily the nominal spacing in the layout.

6. Test Possible Physical Explanations

The authors examine several possible mechanisms.

Electric-field enhancement: FEM simulations show that the electric field is primarily explained by the actual spacing between lines. No additional unexpected linewidth-dependent field enhancement is needed.

Line-edge roughness: Monte Carlo analysis shows that LER can substantially reduce lifetime, especially at small spacing. However, for these structures the degradation is approximately similar across linewidths, so LER does not explain the observed linewidth trend.

Lithography: Optical proximity and flare effects do not produce trends consistent with the measured linewidth changes.

Etching: The strongest evidence supports an etch-related mechanism.

7. Connect Etching to Aspect Ratio

Figures 11–13 on pages 6–7 show relationships among linewidth, feature height, aspect ratio, and etch behavior.

The authors conclude that narrow features receive less sidewall protection from polymer deposition during etching and can experience greater lateral etching.

More lateral etching makes the metal feature wider than intended, which makes the neighboring dielectric spacing smaller.

The resulting chain is approximately:

linewidth → aspect ratio → etch behavior → printed linewidth → actual spacing → electric field → TDDB lifetime

8. Build a Model for Chip-Level Analysis

Each dielectric segment in the layout is characterized by:

• Vulnerable length $L$
• Drawn spacing $S_D$
• Left-hand linewidth $W_L$
• Right-hand linewidth $W_R$

The adjacent linewidths are then used to predict physical geometry, including actual spacing and worst-case aspect ratio.

The authors empirically model characteristic lifetime as:$$\ln \eta =C+D\zeta$$

where $\zeta$ represents the worst-case aspect ratio.

Weibull η and β parameters—and, for the bimodal model, the probability of early failure—are estimated for each dielectric segment.

9. Area-Scale and Combine the Segment Lifetimes

The lifetime distribution of each segment is adjusted according to its vulnerable area.

Individual dielectric-segment failure distributions are then mathematically combined to determine the lifetime distribution of the complete chip.

10. Test the Methodology on FFT Layouts

The authors implement several versions of a radix-2 FFT circuit.

The layouts are labeled:

• L1X: reference metal-3 linewidth.
• L3X: metal-3 lines three times wider.
• L4X: metal-3 lines four times wider.

Figure 19 on page 9 shows that wider metal improves characteristic lifetime, but only modestly at the full-chip level.

Main Findings

The paper reports several important results.

1. TDDB lifetime depends on linewidth in the tested technology.
Characteristic lifetime increases substantially as linewidth increases in the comb test structures.

2. Pattern density does not explain the observed effect.
Test structures with equal density but different linewidth arrangements show different lifetime distributions.

3. Actual geometry matters more than nominal geometry alone.
Fabricated linewidths differ systematically from the layout dimensions, changing the real dielectric spacing.

4. The electric field is principally determined by actual line-to-line spacing.
Finite-element simulations do not show an additional unexplained linewidth-dependent field enhancement.

5. LER degrades TDDB lifetime but does not explain the linewidth dependence in this dataset.
Its modeled effect is approximately common across the tested linewidths.

6. Lithographic explanations are inconsistent with the observed geometry trends.

7. Aspect-ratio-dependent etching is identified as the primary explanation supported by the data.
Increased lateral etching in narrow features reduces physical dielectric spacing and thereby lowers time to failure.

8. Full-chip reliability models therefore need information about adjacent linewidths.
Using only nominal spacing and vulnerable length can miss an important manufacturing-dependent reliability effect.

9. Wider wires do not necessarily yield a proportionally larger chip lifetime.
The FFT experiments show only a small full-chip improvement because rerouting can increase vulnerable dielectric area.

Technical Significance

The main technical contribution is a shift from a purely layout-spacing-based TDDB model toward a manufacturing-aware geometric reliability model.

A conventional model might treat dielectric lifetime as primarily:$$\text{Lifetime}=f(S)$$

The results of this paper imply that a more realistic representation for the tested process is closer to:$$\text{Lifetime}=f(S_D,W_L,W_R,\text{manufacturing geometry})$$

because neighboring linewidths influence the printed spacing.

This is important for reliability simulation because it connects three traditionally separate levels of analysis:

• Physical manufacturing variation
• Interconnect geometry
• Statistical chip-level reliability

The paper also demonstrates why reliability-aware design cannot always work exclusively with drawn dimensions. A nominally identical spacing can correspond to different electrical stress after fabrication.

Industrial Impact

For semiconductor manufacturing and reliability engineering, the results suggest several practical consequences.

First, etch uniformity can become a reliability variable, not merely a dimensional-control variable. An etch process that meets conventional profile or trench-fill requirements may still introduce linewidth-dependent spacing differences that influence TDDB.

Second, design rules or reliability tools that use only nominal spacing can potentially underestimate or mischaracterize the risk associated with specific interconnect geometries.

Third, increasing metal width globally is not necessarily an efficient reliability solution. Wider lines consume routing resources. The authors’ FFT study shows that rerouting can increase vulnerable area enough to cancel part of the local TDDB advantage.

The paper therefore points toward process optimization and geometry-aware reliability modeling rather than a simple “use wider wires” strategy.

Why the Paper Matters

The paper demonstrates that interconnect reliability is not solely determined by what appears in the design database. Fabrication changes the geometry, and those changes can materially alter dielectric lifetime.

That distinction becomes especially important as dimensions shrink and the difference between drawn and manufactured geometry becomes a larger fraction of the available dielectric spacing.

The broader contribution is methodological: instead of treating test-structure reliability data as universally applicable to all structures with the same nominal spacing, the authors show how to map test results through manufacturing geometry into a full-chip reliability calculation.

The study therefore provides a bridge from process-dependent physical effects to circuit-scale lifetime prediction.

Limitations and Scope

Several limitations are either stated directly by the authors or follow from the scope of their methodology.

Technology specificity: The experimental structures were fabricated in a 45 nm Cu/low-k process. Numerical relationships between linewidth, aspect ratio, etching, and Weibull parameters should not be assumed to transfer directly to newer technologies.

Process maturity: The authors explicitly note that the wafers were produced while the process was under development and was not yet mature or fully optimized. Some of the relationships observed between aspect ratio and reliability parameters may therefore be process-specific.

Limited linespace variation: The authors state that their data exhibit stronger dependence on aspect ratio than on spacing, possibly because the dataset does not contain enough spacing variation to independently extract the usual electric-field-model parameters with confidence.

Unresolved statistical interpretation: Curvature in the measured Weibull plots can be modeled either as a bimodal failure population or as the consequence of random die-to-die variation. The paper analyzes both alternatives rather than conclusively proving which is physically correct.

Physical mechanism interpretation: The attribution to lateral, aspect-ratio-dependent etching is supported by measured geometry and consistency with the observed trends, but some microscopic details—such as polymer protection of wider sidewalls—are presented as possible explanations rather than directly measured mechanisms.

Full-chip demonstration: Chip-level results are demonstrated using several implementations of a radix-2 FFT circuit. Broader circuit classes could exhibit different routing-area tradeoffs.

Advanced-node patterning: The authors explicitly note that technologies using double patterning require additional information. Patterning order and alignment can create multimodal physical spacing distributions, so layout segments would need additional labels and corresponding process-characterization data.

Concise Technical Abstract

Bashir and Milor investigate the dependence of Cu/low-k backend dielectric TDDB on metal linewidth using 45 nm comb test structures designed to vary linewidth and pattern density independently. TDDB characteristic lifetime increases with linewidth, while comparison of equal-density structures indicates that pattern density is not the principal cause. SEM measurements show systematic linewidth-dependent deviations between drawn and printed geometries. FEM analysis indicates that electric field is governed primarily by actual line spacing, while modeled line-edge roughness and lithographic effects do not explain the observed linewidth dependence. The experimental trends are instead consistent with aspect-ratio-dependent etching and increased lateral etching of narrow features, which reduces physical dielectric spacing and shortens lifetime. The authors incorporate the effect into full-chip reliability analysis by extracting vulnerable length, drawn spacing, and adjacent linewidths for each dielectric segment, using these quantities to estimate physical geometry and Weibull parameters, area-scaling individual segment distributions, and combining them into a full-chip lifetime distribution. FFT layout experiments show that wider wires improve local TDDB lifetime but provide only modest chip-level gains because rerouting can increase vulnerable area.