Built-In Self-Test Methodology With Statistical Analysis for Electrical Diagnosis of Wearout in a Static Random Access Memory Array

Full citation: Kim, W., Chen, C.-C., Kim, D.-H., and Milor, L. (2016). “Built-In Self-Test Methodology With Statistical Analysis for Electrical Diagnosis of Wearout in a Static Random Access Memory Array.” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24(7), 2521–2534. DOI: 10.1109/TVLSI.2015.2513369. 

Plain-Language Overview

When an SRAM memory begins failing in the field, determining why it failed can be difficult. A defective memory cell may have suffered gate-oxide breakdown, interconnect dielectric breakdown, electromigration, stress-induced voiding, or transistor aging from bias temperature instability. Several of these mechanisms can produce almost identical electrical symptoms.

Traditionally, engineers may resort to physical failure analysis: opening or deprocessing the chip and examining the suspected defect. That procedure can be expensive, slow, and unsuccessful when the physical defect is difficult to locate.

This paper proposes a different strategy. The SRAM contains a specialized built-in self-test (BIST) system that periodically performs electrical measurements. It identifies failing cells, determines the physical location and electrical form of the defect, and then uses statistical analysis of failures across many cells to infer which physical wearout mechanism is responsible when electrical testing alone cannot distinguish the cause.

The methodology covers a broad set of mechanisms:

• Gate time-dependent dielectric breakdown (GTDDB)
• Back-end time-dependent dielectric breakdown (BTDDB)
• Electromigration (EM)
• Stress-induced voiding (SIV)
• Negative bias temperature instability (NBTI)
• Positive bias temperature instability (PBTI)

The important innovation is the combination of two levels of diagnosis:

1. Electrical diagnosis determines whether the cell contains a short, open, or threshold-voltage degradation and identifies its physical location.
2. Statistical diagnosis separates mechanisms that create the same electrical signature by comparing observed field-failure distributions with reliability simulations based on realistic workload and temperature conditions. 

What Problem the Paper Addresses

Error-correcting codes and spare SRAM rows can allow a processor to continue operating after individual memory cells fail. But those techniques do not necessarily explain what physical wearout mechanism is producing the failures.

That information matters for several reasons.

If field failures occur more quickly than predicted, manufacturers need to determine whether the dominant cause is:

• transistor aging,
• gate-dielectric breakdown,
• interconnect dielectric breakdown,
• electromigration,
• stress-induced voiding,
• or another mechanism.

Knowing the dominant mechanism can influence:

• fabrication-process improvements,
• product qualification,
• reliability models,
• redundancy requirements,
• workload restrictions,
• voltage and thermal management.

Physical failure analysis can provide this information, but the paper notes that it is costly and time-consuming and can have a low success rate.

Electrical diagnosis is faster, but it has another problem: different physical mechanisms sometimes create exactly the same electrical fault.

For example:

• GTDDB and BTDDB can both produce the same resistive-short location.
• EM and SIV can both create an open circuit at the same via or contact.

No electrical test can unambiguously tell these mechanisms apart if the physical fault location and electrical signature are identical.

The paper addresses this ambiguity by combining electrical BIST results with simulated distributions of where different mechanisms are statistically expected to fail.

Questions the Paper Answers

The study examines questions including:

• Can SRAM BIST identify not just faulty cells but the physical locations of wearout defects inside them?
• Can short faults, open faults, and BTI degradation be distinguished electrically?
• How can gate-dielectric and back-end dielectric breakdown be separated when both create the same short?
• How can electromigration and stress-induced voiding be separated when both create the same open?
• Can current measurements detect wearout before every degradation mechanism causes a conventional functional fault?
• What test patterns are required to distinguish specific defect locations?
• How does process variation affect fault detectability?
• Can statistical field-failure distributions be compared with reliability simulations to estimate the relative frequency of different mechanisms?
• How sensitive is that statistical diagnosis to an incorrect assumption about the processor use scenario?
• What BIST area and test-time overhead are required?

Key Technical Terms and Definitions

Built-In Self-Test

Built-in self-test (BIST) is hardware integrated into the chip that generates test patterns, applies them to the SRAM, and analyzes the responses.

The proposed system contains:

• A test-pattern generator
• Test-address counters
• Current-sensing circuits
• Digital fault-detection logic
• An output-response analyzer
• Registers containing diagnosis results
• An active/repair block

The architecture is shown in Figure 6 on page 4. 

Electrical Diagnosis

Electrical diagnosis attempts to determine the type and location of a fault by observing electrical behavior rather than physically inspecting the chip.

The paper uses combinations of:

• Bitline current
• Bitline-bar current
• VDD current
• Ground-network current
• Read/write functional values
• Retention behavior
• Transition behavior

Gate Time-Dependent Dielectric Breakdown

GTDDB occurs when the transistor gate dielectric progressively develops conductive paths.

The paper models dominant failures as resistive leakage paths from:

• Gate to source
• Gate to drain

Eight possible GTDDB locations, G1–G8, are defined in the SRAM model.

Back-End Time-Dependent Dielectric Breakdown

BTDDB occurs in the insulating dielectric between interconnect conductors.

Breakdown creates a resistive bridge between normally isolated electrical nodes.

The physical SRAM layout used in the study contains several potential BTDDB sites, including faults both within a cell and between neighboring cells.

Electromigration

Electromigration (EM) is transport of conductor atoms caused by electrical current.

Over time it can thin a via or contact and eventually produce a high-resistance or open connection.

EM depends strongly on current density and conductor geometry.

Blech Length

The Blech length describes the minimum conductor-length/current-density condition associated with electromigration voiding.

For the analyzed SRAM, only selected contacts—O2, O5, and O9—are considered susceptible to EM under the geometry assumptions.

Stress-Induced Voiding

Stress-induced voiding (SIV) results from thermomechanical stress between interconnect materials and surrounding dielectric.

It can create the same type of via/contact open circuit as EM.

Unlike EM, however, its physical acceleration is principally linked to mechanical and temperature-related stress rather than current transport.

Bias Temperature Instability

BTI gradually changes transistor threshold voltage.

The paper includes:

• NBTI in the two pMOS transistors
• PBTI in four nMOS transistors

NBTI and PBTI do not necessarily produce immediate stuck-at failures. Instead, they progressively weaken SRAM stability and timing.

Static Noise Margin

Static noise margin (SNM) measures how much disturbance an SRAM cell can tolerate without losing its stored state.

For the modeled degradation level, the authors report that a 30% threshold-voltage shift produces:

• Approximately 7.35% reduction in read SNM for NBTI
• Approximately 10.52% reduction in read SNM for PBTI

A 30% PBTI shift in an access transistor can also increase cell access time by approximately 11.1%. 

Resistive-Short Fault

A resistive short represents a dielectric-breakdown path connecting nodes that should be electrically isolated.

The simulation examples use 10 Ω for the modeled bridging faults during functional-test verification.

Resistive-Open Fault

A resistive open represents a degraded via/contact.

The simulation examples use 10 MΩ for severe open faults during functional-test verification.

Fault Group

Different physical mechanisms may produce electrically identical defects.

The paper therefore groups faults according to their electrical location:

• Four short groups, SG1–SG4, for GTDDB/BTDDB
• Three open groups, OG1–OG3, where EM/SIV overlap

BIST can identify the group, while statistical analysis estimates the underlying physical mechanism.

Use Scenario

Reliability depends on how the processor containing the SRAM is used.

The paper evaluates use profiles including:

• Corporate
• Gaming
• Office Work
• General Usage

Each consists of different fractions of:

• Active operation
• Standby
• Powered-off time

These scenarios change current, temperature, and electrical stress and therefore change the predicted distribution of failure sites. 

Workflow

1. Map physically feasible wearout locations

The methodology starts with the SRAM schematic and physical layout.

Instead of inserting arbitrary circuit faults, the authors identify locations where actual wearout physics can realistically create:

• Gate-oxide shorts
• Interconnect-dielectric shorts
• Via/contact opens
• BTI-related transistor degradation

Figures 2 and 3 on page 2 map the electrical and layout locations of these faults. 

2. Model lifetime for each fault mechanism

GTDDB and BTDDB are represented statistically with Weibull lifetime distributions.

EM and SIV also receive location-dependent lifetime models.

Stress varies across SRAM cells according to:

• Logic activity
• Stored state
• Current density
• Temperature
• Physical geometry
• Processor workload

Consequently, different sites of the same nominal mechanism need not have the same failure probability.

3. Obtain workload-dependent reliability distributions

The reliability simulator evaluates SRAM embedded in a LEON3 microprocessor under realistic benchmarks and use scenarios.

This produces expected distributions of failures among:

• Individual short groups
• Individual open groups

Even when two mechanisms create exactly the same electrical fault, their relative probabilities across several fault locations differ.

That difference is what ultimately enables statistical separation.

4. Periodically run BIST

The customized BIST is designed to operate while the memory itself is not being used.

Its circuits are connected in parallel with the normal memory paths so that normal SRAM timing is not directly placed in series with the diagnostic circuitry. 

5. Divide the SRAM into local comparison regions

Current measurements are sensitive to the resistance and capacitance between a cell and the sensing circuit.

A cell physically far from its reference could therefore appear different even when both are healthy.

To reduce this problem, each bank is divided into 64 subblocks. The test cell and reference cell are selected from corresponding nearby subblocks in paired banks.

The maximum allowed path-length mismatch in the demonstrated design is 110 μm. 

6. Find healthy reference cells

The first test scans cells and compares their currents pairwise between two banks.

If two cells show essentially matching behavior, they can serve as references.

Cells that exhibit excessive current differences are placed into a suspect set.

After a reliable reference is found, each suspect is compared against that reference to determine which cell is actually abnormal.

7. Perform wearout screening

The current-sensing circuitry contains:

• A current subtractor
• A current amplifier
• A current digitizer
• Programmable reference-current generation

Different tests use different current thresholds.

This initial screening detects most short and open failures from abnormal bitline currents. 

8. Run targeted diagnosis patterns

Once a cell is classified as faulty, a sequence of specialized tests identifies the physical location.

The paper’s flow includes tests such as:

• CF1 and CF2 — coupling-fault tests
• TV1 and TV2 — VDD variation tests
• TG1 and TG2 — ground variation tests
• TF1, TF2, TF3, TF4 — transition-fault tests
• DRF1 and DRF2 — data-retention tests

The complete decision flow is shown in Figure 9 on page 6, while Table III on page 7 maps the patterns to the fault locations they detect. 

9. Detect VDD-related shorts

Some dielectric-breakdown paths connect an internal signal node to the supply.

During appropriate read/write states, these faults cause abnormal current from VDD toward ground.

The BIST temporarily uses a higher-resistance supply test path so that the resulting VDD disturbance is easier to detect.

10. Detect ground-related shorts

Other shorts connect signal nodes toward ground.

Different logic states activate these faults and produce measurable ground-current differences.

Specific test patterns therefore distinguish short groups according to when the leakage path conducts.

11. Identify coupling defects

BTDDB can create faults between structures belonging to adjacent cells.

Special write/read sequences reveal abnormal interactions between victim and aggressor cells.

For example, the B8 coupling fault is diagnosed by temporarily disabling the sense amplifier and observing a distinctive inversion in digitized bitline and bitline-bar behavior.

12. Distinguish open defects

Transition-fault tests detect cells in which an open prevents the intended state transition.

Data-retention tests then distinguish open locations that create otherwise similar transition failures.

This allows the method to identify the specific via/contact site.

13. Diagnose BTI separately

BTI-related cells may not show the same large leakage-current changes as dielectric shorts or opens.

They are therefore handled in later tests designed around weakened read/write characteristics and threshold-voltage degradation.

Because HCI also produces threshold-voltage changes, the authors note that a methodology capable of diagnosing BTI-type threshold degradation could in principle also diagnose HCI-induced threshold shifts. 

14. Repair the identified cell

The BIST system passes fail addresses to an active/repair block.

Redundant SRAM arrays can then remap cells or rows containing diagnosed failures.

The diagnostic method therefore complements the memory’s existing fault-tolerance architecture.

15. Aggregate field failures by physical fault group

Across a large number of failing SRAM cells, the system records how many failures occur in:

• SG1
• SG2
• SG3
• SG4

and:

• OG1
• OG2
• OG3

These measured fractions form the field-data input to the statistical analysis.

16. Obtain predicted group distributions from reliability simulation

The simulator independently calculates the expected group probabilities if failures came entirely from:

• GTDDB
• BTDDB
• EM
• SIV

The calculations include each site’s Weibull lifetime and the workload/thermal stress of SRAM cells.

Figure 17 on page 12 shows how these distributions change with mechanism mixture and processor use scenario. 

17. Estimate the GTDDB/BTDDB mixture

Let ζ represent the fraction of relevant short failures caused by GTDDB.

The measured probability of failure in short group k is modeled as:P_k,chip​=ζ*P_k,GTDDB​+(1−ζ)*P_k,BTDDB​.

The set of measured group frequencies is fitted to the corresponding simulated distributions to estimate ζ.

Thus, even though a particular short cannot individually be labeled GTDDB or BTDDB, the population of shorts can be statistically decomposed.

18. Estimate the SIV/EM mixture

Similarly, let λ represent the SIV fraction among the ambiguous open faults.

For open group m: P_m,chip​=λ*P_m,SIV​+(1−λ)P_m,EM​.

Matching the field-data distribution with simulated group distributions estimates the SIV-versus-EM proportions. 

Main Findings

Electrical BIST can diagnose much more than a conventional pass/fail memory test

The proposed test does not stop after determining that an SRAM bit failed.

It identifies whether degradation is associated with:

• A resistive short
• A resistive open
• A BTI-like threshold-voltage change

and determines the specific physical fault location in the modeled SRAM layout.

This creates much richer failure-analysis data than a simple fail address.

Some wearout mechanisms are fundamentally indistinguishable on a single-cell electrical basis

One of the paper’s most important conclusions is that no clever test pattern can uniquely identify a physical mechanism when two mechanisms create exactly the same electrical connection at the same location.

This occurs for:

• GTDDB versus BTDDB at several short sites
• EM versus SIV at selected via/contact open sites

The authors address this limitation explicitly rather than pretending electrical diagnosis can always provide a unique physical cause.

Population statistics provide information unavailable from an individual failure

Although a single short may be ambiguous, GTDDB and BTDDB do not produce the same relative distribution of shorts across all physical locations.

Likewise, EM and SIV do not produce identical relative distributions of open faults.

Aggregating many BIST results therefore provides information that a single faulty cell cannot provide.

This is the central statistical contribution of the paper. 

Workload information is important to statistical diagnosis

Failure-location probabilities depend on stress, and stress depends on processor use.

Using the wrong use scenario in the reliability simulator creates errors in the estimated physical-mechanism mixture.

Figure 18 on page 13 demonstrates this by treating Corporate as the true scenario while using Gaming simulation data for diagnosis.

The result means that field-failure diagnosis benefits from knowledge of how the product was actually operated. 

Reliability-model uncertainty also affects mechanism separation

The statistical method assumes that simulated probabilities for GTDDB, BTDDB, EM, and SIV approximate the real distributions.

The authors therefore perturb these probabilities statistically and study the resulting error in the estimated mixture parameters ζ and λ.

Figure 19 on page 13 shows that uncertainty in reliability simulation propagates directly into uncertainty in the inferred mechanism fractions. 

Process variation reduces the detectable resistance range

Fault detection is easier when healthy cells behave uniformly.

Process variation broadens the current and timing distributions of good SRAM cells, making weak wearout faults harder to distinguish from normal variation.

Table XI on page 12 compares detectable resistance ranges with and without 10% process-variation corners.

The authors identify a particularly important threshold: a threshold-voltage variation of approximately 34.51% makes the B7 fault undiagnosable in their model.

When variation remains below that critical level, the proposed BIST can distinguish all modeled wearout fault classes within its assumed detection ranges. 

The customized BIST area overhead is modest

For the demonstrated 128-kb SRAM, the customized BIST circuitry occupies approximately:

0.67% of the SRAM area.

The authors also consider a much larger 32-Mb implementation. In that example:

• Conventional memory-BIST area is approximately 0.043% of the SRAM.
• The customized diagnostic portion corresponds to approximately 12.08% of the conventional BIST circuitry.

Because memory capacity increases faster than the diagnostic hardware requirement, percentage overhead generally decreases for larger arrays. 

The diagnostic runtime is short for the demonstrated fault population

For the 128-kb SRAM, the authors calculate a worst-case test time of approximately:

0.632 seconds

for a test population containing 384 faulty cells, comprising:

• 144 short faults
• 176 open via/contact faults
• 32 NBTI degradation faults
• 32 PBTI degradation faults

This makes periodic diagnosis potentially practical during periods when SRAM is not actively serving requests. 

Pairwise comparison helps suppress common leakage effects

The sensing system compares neighboring/reference cells rather than applying one absolute current threshold to every memory location.

This makes the method more tolerant of the large background leakage expected in scaled processes because common leakage contributions can partially cancel.

However, the authors acknowledge that more advanced technologies may require additional reference cells or adjusted trigger limits.

The test infrastructure is designed not to sit directly in the normal timing path

The diagnostic circuits are connected in parallel with normal data lines and are intended to operate periodically when memory is not serving regular accesses.

That minimizes direct interference with normal SRAM performance, although the authors still emphasize the need for timing-closure verification.

Technical Significance

The most important contribution is the integration of electrical failure analysis and statistical reliability modeling.

Traditional memory BIST typically answers questions such as:

• Does this address work?
• Should this row be replaced?

This paper goes substantially further:

• Where inside the SRAM cell is the physical defect?
• Is it an open, short, or parametric degradation?
• Which physical wearout mechanisms could cause it?
• Across the entire failing population, how frequently is each mechanism occurring?

This turns BIST into a potential field failure-analysis instrument, rather than merely a manufacturing test or repair tool.

A second technical contribution is the explicit use of layout-feasible defect models. The test patterns are derived from shorts and opens that the physical SRAM geometry can realistically produce rather than from an unrestricted abstract fault list.

A third contribution is the recognition that failure diagnosis sometimes requires volume statistics. When two mechanisms are electrically indistinguishable in an individual cell, the authors do not rely on an arbitrary classification. Instead, they estimate mechanism fractions from population distributions.

Finally, the work creates a bridge between field data and predictive reliability simulation. Field BIST provides empirical failure-location distributions, while the simulator explains what distributions should be expected from different physical mechanisms and workloads.

Industrial Impact

Source-supported implication: The methodology could reduce dependence on destructive physical failure analysis when investigating SRAM wearout.

Potential industrial applications include:

• Field-return diagnosis
• SRAM reliability monitoring
• Processor cache health monitoring
• Process-development feedback
• Failure-mechanism ranking
• Reliability-model calibration
• Qualification of redundancy requirements
• Identification of unexpectedly dominant wearout mechanisms

Because modern processors contain large amounts of SRAM, memory arrays can provide a statistically rich source of wearout data.

Interpretation: A manufacturer could aggregate BIST results from many deployed products and monitor whether the observed fault-location distribution begins shifting toward a particular wearout mechanism.

For example, a growing BTDDB fraction could indicate a back-end dielectric problem, while an abnormal increase in EM-related failures might suggest current-density or interconnect-design concerns.

This could make product SRAM serve as a distributed reliability monitor for the manufacturing technology itself.

Why the Paper Matters

Failure diagnosis usually faces a tradeoff.

Physical analysis can potentially reveal the actual defect but is slow, destructive, expensive, and not always successful.

Electrical testing is fast and scalable but may reveal only symptoms.

This paper shows that combining electrical testing with statistical physical models can recover part of the information normally associated with physical failure analysis.

Its most important conceptual insight is that an individual failure may be ambiguous while a population of failures is informative.

A short at one electrical location cannot necessarily tell an engineer whether gate oxide or back-end dielectric failed. But if thousands of shorts appear across multiple sites in a distinctive ratio, the distribution itself contains information about the underlying mechanism.

That approach is particularly suited to SRAM because memory arrays provide very large populations of nearly identical structures from which statistically meaningful field-failure data can be collected.

Limitations and Scope

The paper has several important boundaries:

• The implementation and validation are based on IBM 90-nm technology. Exact thresholds, currents, resistance ranges, area estimates, and failure distributions are technology-specific. 
• The study targets SRAM-cell wearout, not failures inside the BIST or peripheral circuitry.
• The authors assume BIST/peripheral structures are less vulnerable because they use looser design rules and the diagnostic circuitry is normally powered down.
• GTDDB analysis largely excludes the access transistors because their modeled GTDDB lifetime is much longer under the assumed stress conditions.
• Only physically selected back-end fault sites from the particular SRAM layout are modeled. A different cell layout may require modified test patterns.
• The test examples use simplified severe-fault resistance values such as 10 Ω for bridges and 10 MΩ for opens, although later analysis studies broader detectable resistance ranges.
• Electrical testing cannot uniquely distinguish GTDDB from BTDDB or EM from SIV when the mechanisms produce the same physical fault location.
• Statistical separation therefore depends on the accuracy of the reliability simulator.
• Incorrect workload/use-scenario assumptions can bias the estimated mechanism proportions.
• Device-model errors and process-model errors also propagate into the inferred distributions.
• Current diagnosis is sensitive to interconnect path mismatch, requiring partitioning into local subblocks and reference-cell selection.
• The 110-μm path mismatch constraint is specific to the modeled implementation.
• Process variation narrows the range over which faults are distinguishable.
• At approximately 34.51% threshold-voltage variation, the modeled B7 fault becomes undiagnosable. 
• Advanced nodes with greater OFF-state leakage may require more reference cells and different thresholds.
• Analog sensing circuits are more process-dependent than ordinary soft BIST IP and require recharacterization for new technologies.
• Multiple simultaneous faults interacting within a single cell are not the central focus of the presented classification flow.
• HCI does not receive its own separate statistical fault-location model; the authors state that threshold shifts from HCI could be diagnosed through the same class of methods used for BTI.
• Self-heating is not incorporated into the demonstrated 90-nm analysis. The authors specifically identify it as necessary when extending the framework to more advanced nodes. 
• The paper is simulation- and design-validation-based rather than a published large-scale silicon field trial of the complete statistical diagnosis procedure.

Concise Technical Abstract

This paper presents a built-in self-test and statistical-analysis framework for electrical diagnosis of SRAM wearout caused by gate time-dependent dielectric breakdown, back-end dielectric breakdown, electromigration, stress-induced voiding, NBTI, and PBTI. Physically feasible short, open, and threshold-voltage-degradation sites are identified from a 6T SRAM schematic and layout. A customized BIST architecture combines pairwise current sensing of bitlines and power/ground networks with digital read/write, coupling, transition, and retention tests to locate defective cells and identify their physical fault sites. For electrically ambiguous failures—GTDDB versus BTDDB shorts and EM versus SIV opens—the measured relative frequency of faults across groups of physical locations is matched to workload-dependent Weibull failure distributions generated by a reliability simulator. Mixture parameters estimate the relative contribution of each underlying mechanism. The methodology is evaluated using IBM 90-nm designs and realistic processor use scenarios. Process variation reduces fault detectability, with a modeled threshold-voltage variation of approximately 34.51% making one BTDDB coupling fault undiagnosable. The customized BIST occupies approximately 0.67% of a 128-kb SRAM, and the calculated worst-case test time for 384 modeled faulty cells is 0.632 s. The work demonstrates that electrical BIST combined with population-level statistical analysis can provide mechanism-oriented field failure diagnosis without relying exclusively on destructive physical failure analysis.