System-Level Modeling of Microprocessor Reliability Degradation Due to Bias Temperature Instability and Hot Carrier Injection

Full citation: Chen, C.-C., Liu, T., and Milor, L. (2016). “System-Level Modeling of Microprocessor Reliability Degradation Due to Bias Temperature Instability and Hot Carrier Injection.” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24(8), 2712–2725. DOI: 10.1109/TVLSI.2016.2520658. 

Plain-Language Overview

Transistors inside a microprocessor gradually become weaker as the processor ages. Two important causes are bias temperature instability (BTI) and hot-carrier injection (HCI). Both can change transistor threshold voltage, reduce drive strength, increase logic delay, and eventually cause the processor to violate its timing requirements.

Predicting this at the level of an entire processor is much harder than predicting aging for one transistor. Different transistors experience different logic states, switching frequencies, temperatures, workloads, and amounts of idle time. Memory cells also fail differently from ordinary logic: processor logic is mainly limited by timing, while SRAM reliability depends on quantities such as noise margin, read current, and minimum retention voltage.

This paper develops a system-level simulation framework that connects device aging physics to actual processor performance and lifetime. It combines:

• NBTI and PBTI models
• HCI models
• Workload-dependent switching activity
• Device duty cycles
• Processor temperature profiles
• Process variation
• Statistical timing analysis
• SRAM stability analysis
• Error-correcting codes
• Active, standby, and powered-off use scenarios

The methodology is demonstrated on a LEON3 processor and a second 32-bit RISC processor. Rather than declaring failure after a transistor reaches an arbitrary degradation limit, the authors define failure according to actual circuit-level performance requirements: logic fails when timing is violated, and SRAM fails when its critical electrical performance crosses specification limits.

What Problem the Paper Addresses

Device-level BTI and HCI models were already well established when this paper was published, but translating those models into the lifetime of a complete processor remained difficult.

A microprocessor contains hundreds of thousands of logic gates and many thousands of SRAM cells. Each one can experience a different combination of:

• Logic-state probability
• Switching frequency
• Temperature
• Process variation
• Active time
• Standby time
• Recovery time

BTI and HCI are also fundamentally different from catastrophic wearout mechanisms. An interconnect open or short may directly produce failure, whereas BTI and HCI cause gradual performance degradation. Consequently, knowing a transistor’s degradation is not sufficient; engineers must determine whether that degradation actually causes a timing or SRAM-performance failure.

Another challenge is workload extraction. Simulating a complete processor running realistic software using transistor-level or conventional RTL simulation can require impractical amounts of time.

The paper addresses these problems by using FPGA emulation to obtain realistic activity data quickly and then combining those measurements with physical-design, thermal, statistical timing, and SRAM simulations.

Questions the Paper Answers

The study investigates questions including:

• How can device-level BTI and HCI models be translated into complete microprocessor lifetime?
• How can realistic processor workload activity be obtained without months of detailed simulation?
• How do BTI and HCI stress differ electrically?
• How should active, standby, and powered-off periods be incorporated into lifetime estimation?
• How does process variation modify the predicted lifetime distribution?
• How does processor frequency influence lifetime?
• Which use scenarios produce the most severe aging?
• Which SRAM performance quantities are most sensitive to BTI and HCI?
• How can individual SRAM-cell lifetime distributions be converted into complete memory-block lifetime?
• How much does single-bit error correction improve memory lifetime?
• How can logic and memory lifetime distributions be combined into a full-chip lifetime estimate?
• Can the resulting framework support reliability-aware design and less conservative aging guard-bands?

Key Technical Terms and Definitions

Bias Temperature Instability

Bias temperature instability (BTI) changes transistor electrical characteristics while the transistor remains under voltage and thermal stress.

The paper includes both:

• NBTI: negative bias temperature instability, primarily associated with pMOS devices under negative gate stress.
• PBTI: positive bias temperature instability, associated with nMOS devices under positive gate stress.

BTI is modeled primarily through a time-dependent shift in threshold voltage.

Trapping and Detrapping

The BTI model uses a trapping/detrapping description in which defects in the dielectric capture and release charge.

Threshold-voltage degradation depends on:

• Temperature
• Stress time
• Recovery time
• Device duty cycle

The paper incorporates stress and recovery through an effective duty-cycle formulation.

Hot-Carrier Injection

HCI occurs when energetic carriers generated during transistor operation damage the transistor interface or gate dielectric.

HCI can change:

• Threshold voltage
• Transconductance
• Mobility
• Saturation current

Unlike BTI, HCI stress is closely tied to switching activity. Devices experience HCI mainly during signal transitions.

Duty Cycle

Duty cycle represents the fraction of time a transistor remains in a stress-producing logic state.

It is especially important for BTI because long periods in one logic state can cause greater aging, while periods without stress permit some recovery.

Transition Rate

Transition rate measures how frequently a node changes logic state.

It is particularly important for HCI because HCI stress occurs during switching.

The paper’s Figure 2 on page 3 visually contrasts these stress windows: BTI acts according to logic state, while HCI occurs during transition intervals. 

Electrical Stress Profile

The electrical stress profile describes the logic-state probabilities and switching rates of the processor’s internal nodes.

These quantities are obtained from workload execution and subsequently propagated into internal circuit nodes.

Thermal Profile

The thermal profile describes spatial variation in chip temperature.

Because both BTI and HCI depend on temperature, two otherwise identical transistors may age differently if one operates in a hotter processor region.

The temperature map on page 4 illustrates significant block-dependent spatial temperature variation across the LEON3 layout. 

Process Variation

Process variation represents manufacturing differences between transistors or chips.

The paper’s examples model:

• Die-to-die channel-length variation
• Within-die threshold-voltage variation

Both are incorporated into Monte Carlo lifetime analysis.

Static Noise Margin

Static noise margin (SNM) measures how much electrical noise an SRAM cell can tolerate without changing its stored state.

The paper evaluates read SNM as one of the major aging-sensitive SRAM metrics.

Write Margin

Write margin describes how easily the SRAM cell can be forced into a new state during a write operation.

Read Current

Read current, IREAD​, represents the current during a memory read. Because it influences how quickly the bitline changes, it is related to SRAM access speed.

Minimum Retention Voltage

The minimum retention voltage, VDD-min​, is the lowest supply voltage at which an SRAM cell can retain its state reliably.

Aging that raises the required minimum retention voltage reduces SRAM robustness.

Weibull Distribution

The authors represent lifetime statistically with Weibull distributions characterized by:

• η: characteristic lifetime
• β: shape parameter

These distributions allow probabilities of failure and confidence ranges to be calculated instead of treating lifetime as one deterministic number.

Error-Correcting Code

The memory analysis also evaluates a BCH-based code capable of correcting one bit per word.

Seven additional bits are included for each protected word in the modeled memories. ECC changes complete-memory lifetime because a memory does not fail when its first individual bit fails.

Workflow

1. Model BTI and HCI at the transistor level

The framework begins with physical degradation equations.

BTI produces threshold-voltage shifts based on temperature, stress duration, recovery, and duty cycle.

HCI degradation depends on parameters including:

• Transition rate
• Stress time
• Transition duration
• Technology-specific coefficients

2. Implement the processor on an FPGA

Detailed RTL or SPICE simulation of a processor executing complete benchmarks is too slow for extensive reliability analysis.

The authors instead synthesize the processor to an FPGA.

Counters are automatically added to relevant module interfaces to measure:

• State probabilities
• Toggle rates

A benchmark that might require months in more detailed simulation can therefore be exercised on the FPGA in minutes. 

3. Propagate activity into internal nodes

Monitoring every internal signal directly would consume excessive FPGA resources.

The authors therefore collect activity primarily at block interfaces and use a commercial propagation tool to estimate state probabilities and transition rates throughout the internal netlist.

Validation shows that:

• More than 90% of sampled transition-rate estimates have less than 10% error.
• More than 80% of sampled state-probability estimates have less than 15% error.

Errors increase for nodes deeper inside the circuit because propagation uncertainty accumulates. 

4. Generate the chip layout

The synthesized netlist is physically implemented to obtain:

• Cell positions
• RC parasitics
• Interconnect loading

This physical information is necessary for both power and timing analysis.

5. Calculate power and temperature

Circuit activity and RC information feed the power model.

The resulting power distribution feeds the thermal simulator to calculate a spatial temperature map.

The authors use steady-state temperatures for the active and standby conditions and assign the environmental temperature—30 °C—to the powered-off state.

Thermal transients between operating modes are assumed to be short enough to neglect.

6. Apply realistic use scenarios

The paper does not assume processors remain fully active for their entire life.

It evaluates use profiles containing different proportions of:

• Operation
• Standby
• OFF time

The studied scenarios include categories such as:

• Corporate
• Office Work
• Gaming
• General Usage

OFF time is particularly important for BTI because it increases recovery time.

7. Calculate transistor degradation

Each transistor receives a threshold-voltage shift according to:

• Its state probability
• Transition rate
• Temperature
• Use scenario
• Process variation
• Elapsed lifetime

The resulting aging parameters are annotated back into the circuit model.

8. Translate degradation into gate delay

The authors use multivariate adaptive regression splines (MARS) to create gate-delay models.

For a gate containing N transistors, the model includes transistor-specific channel-length and threshold-voltage parameters plus global parameters such as:

• Supply voltage
• Temperature
• Input slew
• RC load parameters

The largest standard cells can therefore require as many as 2N+6=70 model dimensions. 

9. Approximate interconnect loading

The RC interconnect network is reduced to a Pi-model.

Variation-aware input capacitances are used so that loading also changes appropriately with PVT conditions.

This is important because an aging-aware timing model must capture not only transistor delay but also the loading of the wires connecting gates.

10. Perform block-based statistical timing analysis

A timing graph is generated from the gate-level netlist.

For every Monte Carlo sample, the framework:

1. Calculates gate and interconnect delays.
2. Propagates arrival times.
3. Identifies critical paths.
4. Repeats the operation under another variation sample.

This allows the set of critical paths itself to change with PVT and aging.

11. Perform path-based timing analysis

Candidate paths extracted from the block-based stage are evaluated in greater detail.

The authors report that the combined timing engine achieves near-SPICE accuracy while consuming approximately 1% of the SPICE runtime in the validation experiments.

12. Determine logic lifetime

BTI and HCI progressively increase path delay.

A logic block is considered failed when its degraded delay creates a timing violation relative to the required clock period.

The stress time at which this occurs becomes the lifetime for that Monte Carlo sample.

Repeating the analysis gives a statistical lifetime distribution.

13. Analyze SRAM aging

The processor memories use conventional 6T SRAM cells.

Four principal aging-sensitive quantities are simulated:

• Read SNM
• Write margin
• Read current
• Minimum retention voltage

A memory cell is considered failed when one of these performance quantities crosses its specification threshold.

14. Reduce the SRAM simulation burden

It would be computationally prohibitive to run separate Monte Carlo SPICE simulations for every memory cell.

The authors therefore discretize stress into 21 states, ranging from 0% to 100% in 5% steps.

Separate distributions are used for:

• Static stress states for BTI
• Toggle-rate states for HCI

Cells within one state are treated as having equivalent stress.

15. Calculate complete memory lifetime

Cell-level lifetime distributions are converted into:

• Bit failure probability
• Word failure probability
• SRAM-block failure probability

Without ECC, the memory effectively fails when an unprotected word develops an unacceptable bit failure.

With single-bit correction, the probability calculation allows one failed bit in each protected word before the word itself is considered failed. 

16. Combine logic and memory lifetime

Finally, the Weibull distributions for:

• Logic
• Data cache
• Instruction cache
• Register file
• Data tags
• Instruction tags

are statistically combined to estimate the overall processor lifetime.

The final LEON3 results on page 14, Figure 30 combine:

• BTI
• HCI
• Logic failure
• SRAM failure
• ECC
• Use scenario

into a complete system-level lifetime model. 

Main Findings

Workload produces strongly nonuniform transistor stress

Different processor blocks exhibit very different activity patterns.

The state-probability and toggle-rate maps on page 4 show, for example, that instruction and data tag structures have relatively low state probabilities but relatively high transition rates, while blocks such as the divider, multiplier, integer unit, and MMU tend toward higher state probability and lower transition activity.

This matters because BTI and HCI respond to different aspects of workload. 

Processor lifetime decreases as operating frequency increases

Both BTI and HCI eventually increase logic delay.

At a higher processor frequency, the available timing margin is smaller. Less degradation is therefore required before a critical path violates the clock period.

For both the LEON3 and the additional RISC processor, the estimated logic lifetime decreases as operating frequency increases.

Gaming is the most aggressive studied use scenario

Among the LEON3 use cases, Gaming produces the shortest estimated logic lifetime for both BTI and HCI.

The final combined logic-and-memory analysis also identifies Gaming as the shortest-lifetime use case.

Office Work produces the longest overall lifetime in the reported comparison, while General Usage is worse than Corporate because it contains a larger proportion of active operation.

OFF time can increase BTI lifetime through recovery

BTI depends not just on total calendar time but on how that time is divided between stress and recovery.

Powered-off periods increase recovery time and therefore reduce effective BTI accumulation.

This is one reason why realistic use scenarios produce substantially different lifetime estimates even for the same processor.

Critical paths do not all age at the same rate

Different paths contain differently stressed transistors and experience different temperatures.

Consequently, the critical path that limits a processor initially is not necessarily the only path relevant after years of aging and process variation.

The statistical path-selection methodology captures a broader critical-path population than conventional deterministic STA. 

Process variation widens the lifetime distribution

The logic simulations include 10% standard deviation assumptions for:

• Die-to-die channel-length variation
• Within-die threshold-voltage variation

The dotted confidence boundaries in the lifetime figures show that manufacturing variability produces a meaningful range of possible processor lifetimes rather than one fixed result. 

BTI strongly degrades SRAM read stability

For the modeled SRAM cells, BTI has its strongest effect on read SNM.

Minimum retention voltage is also significantly affected.

By comparison, write margin and read current are comparatively insensitive to BTI in the studied conditions. 

HCI affects SRAM differently from BTI

The HCI result is less intuitive.

In the studied SRAM cells:

• Read current degrades.
• Read SNM, write margin, and VDD-min​ may improve in the aggregate curves.
• Much of the non-read-current behavior is statistical, with some cells improving and others degrading.

This occurs because HCI-induced parameter changes can alter the balance between complementary transistors rather than uniformly weakening every SRAM performance metric.

The authors therefore model complete statistical distributions rather than assuming that all SRAM characteristics degrade monotonically. 

Memory stress is highly nonuniform

Not every SRAM cell stores the same value for the same duration or switches at the same rate.

Figures 20 and 21 on page 11 show distributions across the 21 BTI and HCI stress states.

Thus, assigning every SRAM bit one worst-case duty cycle or activity value would misrepresent the actual processor memory.

ECC substantially improves memory lifetime

The modeled BCH code adds seven check bits and corrects one erroneous bit per word.

Without ECC, one bit failure can eventually cause the corresponding unprotected word and memory to fail.

With ECC, one failed bit can be tolerated, significantly reducing word and complete-memory failure probability.

The paper reports a substantial effect of ECC on memory lifetime for both BTI and HCI in the LEON3 and RISC examples. 

Memory reliability can influence complete processor lifetime

The framework does not assume logic is always the lifetime limiter.

Logic and SRAM distributions are calculated independently and then statistically combined.

This allows an SRAM block to become system-limiting under some stress, frequency, or ECC configurations and a logic block to dominate under others.

Use scenario and ECC both have substantial effects on full-chip lifetime

The final LEON3 model at 280 MHz shows that both workload/use scenario and memory error correction materially change overall lifetime.

This demonstrates that reliability is simultaneously influenced by:

• Device physics
• Circuit design
• Software behavior
• Operating frequency
• Memory architecture

rather than being only a technology parameter. 

Technical Significance

The central contribution of the paper is its cross-layer reliability methodology.

The analysis moves through several abstraction levels:

1. Physical BTI/HCI models
2. Transistor threshold-voltage degradation
3. Gate-delay degradation
4. Critical-path timing
5. SRAM electrical stability
6. Memory error probability
7. Complete block lifetime
8. Full microprocessor lifetime

This is technically important because BTI and HCI do not cause an immediate binary failure. Their relevance depends on whether their physical effects eventually violate a circuit specification.

A second contribution is the use of FPGA emulation to obtain realistic activity for a large processor. The approach makes workload-aware aging analysis practical without requiring months of detailed processor simulation.

A third contribution is the simultaneous treatment of logic and memory. Many reliability analyses evaluate one or the other, but an actual processor fails when either becomes unusable.

The paper also explicitly incorporates ECC when translating SRAM bit failures into system lifetime. Reliability therefore depends on architectural fault tolerance, not simply the intrinsic lifetime of the individual memory cells.

Finally, the statistical timing framework provides a practical connection between process variation and aging. The authors report near-SPICE timing accuracy at roughly 1% of the SPICE computational runtime for their validation designs, making extensive Monte Carlo aging analysis much more feasible. 

Industrial Impact

Source-supported implication: The framework can be applied before fabrication to determine which parts of a processor are likely to become reliability limiting and how lifetime changes with workload, frequency, process variation, and memory protection.

Potential uses include:

• Reliability-aware processor design
• Timing guard-band optimization
• Lifetime-aware clock-frequency selection
• SRAM ECC evaluation
• Workload-aware qualification
• Reliability-sensitive standard-cell optimization
• Thermal management
• Aging-aware memory allocation
• Processor lifetime estimation

The paper specifically notes that lifetime sensitivity to quantities such as supply voltage and threshold voltage can help designers evaluate whether conventional wearout guard-bands are unnecessarily conservative. 

Interpretation: In a commercial design flow, this type of framework could allow reliability to be treated similarly to power and timing during architecture exploration. Instead of simply adding a fixed “aging margin,” designers could estimate how much margin a particular product actually requires for its expected workload.

It could also help distinguish product classes. A processor intended for continuous high-load operation may require different timing margin, cooling, or ECC from a processor expected to spend substantial time in standby or powered off.

Why the Paper Matters

One of the paper’s most important ideas is that processor aging depends on how the processor is actually used.

The same silicon can have different estimated lifetime when:

• Operated continuously or intermittently
• Run at different frequencies
• Used for gaming versus office workloads
• Protected or unprotected by SRAM ECC
• Manufactured at different process points

That means microprocessor reliability cannot be predicted accurately from a transistor lifetime specification alone.

The study also demonstrates that logic and memory require different definitions of failure. Logic is primarily constrained by timing, while SRAM requires electrical stability and access performance. A complete processor reliability model must therefore connect degradation to the specification that actually matters for each block.

This systems perspective is what makes the work important: it changes the question from “How much has the transistor degraded?” to “When does that degradation prevent the processor from operating correctly?”

Limitations and Scope

The methodology has several important boundaries.

• The study concentrates on BTI and HCI. Gate-oxide breakdown, interconnect TDDB, electromigration, stress-induced voiding, and other failure mechanisms are outside the full-chip calculation presented here.
• The results are demonstrated primarily using the LEON3 and one additional 32-bit RISC processor; conclusions about exact lifetimes should not be generalized automatically to other architectures.
• The LEON3 model contains approximately 260,000 gates, about 13 mm² of area, and roughly 0.3–0.5 W of modeled power. The second RISC example contains about 73,000 gates, approximately 7 mm², and roughly 0.1–0.2 W.
• Activity is measured at module interfaces and probabilistically propagated into internal nodes rather than measuring every internal transition directly.
• The propagation method becomes less accurate for deeper internal nodes.
• Thermal behavior is modeled primarily using static temperatures. Transients between operation, standby, and OFF states are assumed negligible.
• No benchmark considered in the study produces thermal runaway.
• The demonstrated process model assumes 10% standard deviations for die-to-die channel length and within-die threshold voltage.
• Correlations among PVT and aging parameters are not included in the reported examples, although the authors describe how correlation could be incorporated.
• Aging itself can change power, IR drop, and temperature, but those feedback correlations are not iteratively modeled in the demonstrated examples. 
• Multiple-input switching is not included in the gate-delay characterization.
• SRAM static stress probability and switching activity are discretized into 21 states rather than modeled continuously.
• SRAM cells assigned to the same stress state are assumed to experience the same stress.
• The memory analysis uses a first-fit memory allocation system; alternative allocation strategies could produce different aging distributions.
• The SRAM failure definition relies on selected specification thresholds for read SNM, write margin, read current, and minimum retention voltage.
• The ECC analysis assumes a particular single-bit-correcting BCH implementation with seven additional bits per word.
• When combining logic and memory distributions, the reported analysis assumes those distributions are uncorrelated. The authors explicitly note that common PVT parameters and use scenarios can create correlations and would require a more detailed joint treatment. 
• The work is predominantly a simulation-based methodology rather than a full silicon lifetime validation campaign.

These limitations mean the framework is most valuable as a methodology for relative design exploration and workload-aware lifetime prediction, while the numerical results depend on the underlying technology, device models, specifications, and architecture.

Concise Technical Abstract

This paper presents a system-level simulation methodology for estimating microprocessor reliability degradation and lifetime due to negative and positive bias temperature instability and hot-carrier injection. FPGA emulation of representative workloads supplies logic-state probabilities and transition rates, which are propagated to internal processor nodes and combined with layout-derived power and thermal profiles to determine transistor-specific electrical and thermal stress. Device-level trapping/detrapping BTI and dynamic HCI models generate time-dependent threshold-voltage shifts under realistic active, standby, and OFF-state use scenarios. For logic blocks, MARS-based variation- and aging-aware gate-delay models and Monte Carlo block/path statistical timing analysis translate transistor degradation into timing-failure distributions. For SRAM, SPICE Monte Carlo analysis evaluates read static noise margin, write margin, read current, and minimum retention voltage across 21 workload-dependent stress states. Cell failure distributions are aggregated into word and block distributions, including the effect of single-bit-correcting BCH ECC. Logic and memory Weibull lifetime distributions are then combined to estimate full-chip lifetime. Experiments with LEON3 and a second RISC processor show decreasing lifetime with increasing operating frequency, substantial workload dependence, the shortest lifetime for the Gaming use scenario, strong BTI sensitivity of SRAM read SNM and retention voltage, HCI sensitivity primarily through read current, and substantial memory-lifetime improvement from ECC. The framework demonstrates how device physics, application activity, temperature, process variation, timing, SRAM stability, and architectural fault tolerance can be integrated into a unified processor-lifetime assessment.