Full citation: Cha, S., Liu, T., and Milor, L. (2017). “Negative Bias Temperature Instability and Gate Oxide Breakdown Modeling in Circuits With Die-to-Die Calibration Through Power Supply and Ground Signal Measurements.” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25(8), 2271–2284. DOI: 10.1109/TVLSI.2017.2683261.
Plain-Language Overview
Integrated circuits age differently even when they are manufactured using the same process. Two chips from the same production line can begin with slightly different transistor dimensions and threshold voltages, and their susceptibility to long-term degradation can also differ.
Normally, engineers characterize mechanisms such as negative bias temperature instability (NBTI) and gate-oxide breakdown (GOBD) using dedicated test structures. Some products also include special on-chip monitors such as ring oscillators or replica critical paths. But those structures have to be designed into the chip before fabrication, making them unavailable for many existing or commercial off-the-shelf devices.
This paper proposes another approach: use the chip’s ordinary power-supply and ground connections as aging sensors.
As transistors degrade, the transient voltage signals on the power and ground rails change slightly. Their peaks shift in both:
- Amplitude
- Time or delay
The authors show that these changes can be related to transistor-level NBTI and GOBD parameters. Once those parameters are calibrated for a particular physical chip, a circuit-level lifetime simulator can estimate that chip’s remaining lifetime.
The important conceptual shift is from process-wide reliability prediction to die-specific reliability prediction. Two nominally identical processors can receive different lifetime estimates because their measured degradation signatures and process parameters are different.
The overall procedure is illustrated in Figure 1 on page 2: device-level aging models and full-chip simulations are first used to establish relationships between degradation and supply/ground signatures; measured chip signatures are then used to extract wearout parameters and estimate lifetime.
What Problem the Paper Addresses
Traditional reliability models are usually calibrated at the process level. Engineers fabricate dedicated reliability structures, stress them under controlled conditions, estimate wearout parameters, and use the resulting model for all products fabricated in that technology.
That approach creates several problems.
First, individual chips vary. Lithography, doping, oxide thickness, threshold voltage, and channel length are not identical from die to die.
Second, NBTI and GOBD themselves are statistical mechanisms. Two otherwise similar transistors may experience different numbers of trapped charges or oxide-breakdown paths after the same stress exposure.
Third, a model derived from dedicated test structures does not automatically account for the actual logic activity and timing characteristics of a complete processor.
Fourth, many chips do not contain aging monitors. Techniques based on ring oscillators, replica paths, or dedicated sensors cannot be retroactively added after tapeout.
The paper therefore asks whether a signal that is already externally accessible—the transient behavior of the VDD and ground rails—can reveal enough information to calibrate aging models separately for each chip.
Questions the Paper Answers
The study addresses several practical reliability questions:
- Can NBTI-induced threshold-voltage degradation be estimated from power/ground bounce?
- Can GOBD-induced leakage degradation also be detected from those same signals?
- How can NBTI and GOBD be separated when both mechanisms are present simultaneously?
- Which model parameters actually need to be extracted from measurements?
- How accurately do supply/ground signal shifts predict circuit path degradation?
- Can the approach work without embedded reliability sensors?
- Can measurements on fabricated processors reproduce trends predicted by simulation?
- How much does chip-to-chip variation change estimated lifetime?
- How much uncertainty is caused by unknown process parameters?
- Can additional process-parameter extraction tighten lifetime confidence bounds?
- Can a calibrated aging model predict the measured delay degradation of the real chip?
Key Technical Terms and Definitions
Negative Bias Temperature Instability
Negative bias temperature instability, or NBTI, is a degradation mechanism that primarily affects pMOS transistors under negative gate bias.
Charge trapping in the gate dielectric causes the transistor threshold voltage to shift over time. As threshold voltage increases in magnitude, transistor drive strength decreases and circuit delay grows.
Eventually, a critical timing path may violate the clock-period requirement.
Trapping–Detrapping Model
The authors use a charge trapping and detrapping model rather than a reaction–diffusion model for NBTI.
The number of electrically active oxide defects is treated statistically and depends on:
- Temperature
- Fermi level
- Stress time
- Duty cycle
The mean number of trapped defects is modeled approximately as μ[n(t)]≈ϕ(T,EF)(A_NBTI+B_NBTI*logt).
The corresponding threshold-voltage shift is proportional to the number of trapped charges.
The two principal NBTI parameters extracted in this study are therefore:
- A_NBTI
- B_NBTI
Duty Cycle
Duty cycle is the fraction of time that a transistor remains under NBTI-producing electrical stress.
Rather than explicitly simulating every stress and recovery event, the method uses an effective Fermi level based on the fraction of time spent in the ON and OFF states.
Gate-Oxide Breakdown
Gate-oxide breakdown, or GOBD, occurs when defects accumulate in the gate dielectric and form conductive paths.
The paper concentrates on soft breakdown, where leakage increases and transistor performance deteriorates before complete hard breakdown.
A circuit can continue operating after initial oxide breakdown, so the occurrence of a breakdown path does not necessarily equal immediate system failure.
Stress-Induced Leakage Current
Stress-induced leakage current, or SILC, is increased gate leakage resulting from oxide defects. It is one observable consequence of gate-dielectric degradation.
Percolation Model
The GOBD model uses a percolation approach in which defects are randomly generated in the gate oxide.
The average defect population depends on voltage, temperature, oxide dimensions, and stress time. As enough defects accumulate, conductive paths form through the dielectric.
The important fitted GOBD parameters identified by the authors are:
- A_GOBD, which strongly influences the average onset time
- β, which strongly affects the variation in breakdown onset
The study finds that another parameter associated with the soft-breakdown resistance model has much less effect on critical-path degradation, so it does not need to be extracted with the same emphasis.
Quantum Point Contact Model
After a soft-breakdown path is generated, its leakage resistance is calculated using a quantum point contact (QPC)model.
The breakdown is represented electrically as a resistance from:
- Gate to source, or
- Gate to drain
The study finds that gate-to-source soft breakdown generally causes greater circuit-delay degradation than gate-to-drain breakdown.
Power/Ground Bounce
When many transistors switch, parasitic resistance and inductance in the power-delivery path cause temporary variations on VDD and ground.
These normally undesirable variations are called power-supply bounce and ground bounce.
The paper uses them as useful diagnostic signatures.
Signature Amplitude Shift
The waveform contains multiple local peaks. Aging changes the height of those peaks.
The difference from the original peak amplitude is denoted as an amplitude shift, ΔA.
Signature Delay Shift
Aging also changes the time at which a peak occurs.
The change in its timing relative to the original waveform is denoted as a delay shift, ΔD.
The authors average changes from multiple maxima and minima rather than relying on a single waveform feature.
Die-to-Die Calibration
Die-to-die calibration means fitting the reliability model separately for each manufactured chip rather than applying one identical set of process-average coefficients to the entire population.
Remaining Lifetime
Remaining lifetime is estimated from circuit timing degradation under the calibrated wearout models.
As aging increases critical-path delay, the chip eventually cannot meet a specified operating frequency. Different frequencies therefore correspond to different predicted lifetimes.
Workflow
1. Start with physical NBTI and GOBD models
The framework first describes NBTI using trapping/detrapping physics and GOBD using defect generation, percolation, and soft-breakdown resistance models.
The purpose is not merely to detect that a circuit has slowed down, but to infer parameters that have physical meaning and can later be used under other workloads.
2. Simulate complete-chip power and ground signatures
Full-chip simulations generate transient VDD and ground waveforms under known test patterns.
The simulations include:
- Process variation
- NBTI degradation
- GOBD degradation
- Supply-voltage variation
- Device-to-device random degradation
The resulting waveforms act as training data connecting transistor-level aging with measurable I/O behavior.
3. Extract waveform peaks
For each supply or ground waveform, the method identifies maxima and minima.
The authors then calculate:
- Average shift in peak amplitude
- Average shift in peak time
Figures 10–12 show how these quantities are extracted and how NBTI and GOBD create distinct populations of amplitude/delay changes.
4. Relate NBTI to signature degradation
The authors construct equations connecting ΔA and ΔD with average threshold-voltage shift.
Simulation across supply voltages of roughly 1.2–2.0 V and temperatures from 25 °C to 125 °C gives a standard error below about 3.5 mV in the extracted threshold-voltage shift.
When the resulting waveform-based extraction procedure is used to recover the underlying NBTI coefficients in simulation, the reported errors in the extracted NBTI parameters are below about 3%.
5. Relate GOBD to signature degradation
For GOBD, simulations relate amplitude and timing changes to the average number of dielectric defects and resulting breakdown paths.
The authors observe that the random location and resistance of individual breakdown paths create increasing sample-to-sample variability, but the reported effect remains below approximately 10% in the illustrated data.
The calibration is performed separately for power and ground behavior so that pMOS- and nMOS-related degradation can be represented.
6. Separate NBTI and GOBD using stress conditions
Neither mechanism can be switched off completely during physical testing.
The authors therefore select conditions where one mechanism is relatively dominant:
- NBTI-focused conditions: approximately 1.4 and 1.6 V
- GOBD-focused conditions: approximately 2.2 and 2.7 V
They then use an iterative procedure.
First, GOBD parameters are estimated from the high-voltage tests. That model is used to estimate how much GOBD was still present in the lower-voltage measurements. The GOBD contribution is subtracted, and the remaining degradation is used to estimate NBTI. The procedure is repeated until the estimates converge.
7. Perform measurements on physical microprocessors
The experimental study uses RISC microprocessor test chips containing approximately 1.4 million transistors in 90-nm CMOS technology.
The nominal operating voltage is 1.2 V, but accelerated-stress voltages between approximately 1.4 and 2.7 V are applied.
Nine chips are analyzed for calibrated lifetime prediction, and each is subjected to approximately 15,000 seconds of testing.
8. Measure NBTI degradation
NBTI experiments use voltages of 1.4, 1.6, and 1.8 V and temperatures spanning approximately 40–120 °C.
A static input is used during stress to suppress HCI associated with switching. A dynamic test pattern is subsequently applied to generate measurable ground bounce.
9. Improve oscilloscope resolution
Because the degradation-induced waveform changes are extremely small, the authors average 512 measurements at corresponding time points.
Signals are then filtered to retain components approximately between 10 MHz and 1 GHz.
The procedure provides reported timing resolution down to approximately 0.2 ps, making small aging-related temporal shifts observable.
10. Measure GOBD degradation
For the GOBD study, processors are stressed around 2.2 V and at different temperatures.
Higher temperature produces greater waveform degradation.
Ground signatures are primarily associated with nMOS behavior, while power-supply signatures provide information about pMOS degradation. Both are therefore required to estimate the complete GOBD effect.
11. Run statistical timing analysis
The chip-specific NBTI and GOBD parameters are inserted into a timing and lifetime simulator.
The analysis evaluates approximately the top 400 critical paths, including corresponding clock paths, to determine how degradation changes system timing with stress time.
12. Estimate lifetime versus operating frequency
A chip fails the timing requirement when aging pushes path delay beyond the permitted clock period.
The resulting lifetime is therefore calculated as a function of operating frequency.
Because each physical chip receives its own wearout coefficients, different chips produce different lifetime-versus-frequency curves.
13. Extract process parameters as well
Wearout calibration alone still leaves considerable uncertainty because initial process parameters also influence timing.
The authors therefore estimate four additional chip-level quantities:
- Average nMOS channel length
- Average pMOS channel length
- Average nMOS threshold voltage
- Average pMOS threshold voltage
Delay and transition-time measurements from nine outputs provide 18 observations.
A Taguchi orthogonal-array experiment and linear regression are used to infer the four process parameters.
14. Recalculate lifetime confidence bounds
After the process parameters are extracted, statistical timing is repeated.
This substantially narrows the lifetime confidence intervals because uncertainty associated with die-to-die process variation has been removed from the prediction.
Main Findings
Power and ground bounce correlate strongly with timing degradation
The central experimental premise works: shifts in the supply/ground waveform are meaningfully correlated with critical-path delay changes.
For the NBTI study, the correlation between path delay degradation and the ground-bounce amplitude/delay characteristics is considerably stronger than the corresponding correlation with conventional static IDDQ in the authors’ analysis.
This supports the use of transient supply behavior as a reliability indicator.
The NBTI extraction is relatively insensitive to moderate model error in ϕ(T,E_F)
The authors perturb the assumed ϕ(T,E_F) term by ±10% and ±20%.
The resulting ground-bounce/path-delay correlation changes by less than about 4.2%.
They therefore conclude that estimating A_NBTI and B_NBTI is sufficient for the proposed calibration approach even if the theoretical ϕ(T,E_F) term is not exact.
NBTI model parameters can be recovered accurately in simulation
When known NBTI parameters are inserted into full-chip simulations and then re-extracted using the supply/ground signatures, the resulting parameter errors are reported as below approximately 3%.
This provides simulation-level evidence that the inverse calibration problem is well conditioned under the modeled test conditions.
GOBD leaves a different electrical signature from NBTI
NBTI raises threshold voltage and generally reduces transistor drive current.
GOBD creates new leakage paths and reduces effective dielectric resistance.
These mechanisms affect the amplitude and timing of the supply/ground waveform differently, especially when voltage stress is selected to favor one mechanism over the other.
That difference enables the iterative separation procedure.
GOBD sensitivity is dominated by particular model coefficients
The simulations show that variations in A_GOBD and β strongly affect critical-path delay.
By contrast, modest variation in the resistance-model parameter examined by the authors has little influence on the final delay.
This reduces the number of parameters that must be estimated experimentally.
Higher temperature accelerates both observable degradation mechanisms
In both NBTI- and GOBD-oriented measurements, higher-temperature stress produces larger waveform changes.
For GOBD, the supply-side degradation is reported as slightly larger than the ground-side degradation, with the difference increasing at higher temperatures.
Lifetime differs from chip to chip
Figure 23 shows distinct median lifetime-versus-frequency curves for individual processors after extracting each chip’s NBTI and GOBD parameters.
The paper specifically notes that the extracted NBTI coefficients affect the slope of lifetime with operating frequency. Some chips are therefore substantially more sensitive to increases in frequency than others.
This is one of the study’s most important findings: a process-average model conceals chip-specific reliability behavior.
Process variation has a major impact on lifetime uncertainty
Before individual process parameters are known, the predicted lifetime curves have very wide confidence intervals.
The uncertainty comes from the combination of:
- Die-to-die parameter differences
- Within-die variation
- Randomness in the wearout mechanisms
The authors show that extracting mean channel length and threshold voltage for each die greatly tightens those bounds.
Unmodeled timing errors are relatively small after calibration
Even after process-parameter extraction, measured and simulated delays are not identical because some parasitics and parameters are omitted.
The paper reports that measured delays are about 2 ps larger on average, with an approximately 10.4-ps standard deviation for the remaining unmodeled error.
When this uncertainty is added back into the lifetime analysis, it has comparatively little effect relative to the process uncertainty removed by calibration.
Calibrated simulation agrees with measured circuit degradation
The final validation compares measured output-path degradation with simulation using NBTI and GOBD parameters extracted from the supply and ground signals.
The comparison is performed for:
- A BTI-dominant case around 40 °C and 1.4 V
- A GOBD-dominant case around 120 °C and 2.7 V
The paper reports good agreement between measured and predicted delay degradation.
The experimental chip-to-chip spread is modest
The authors note that the nine evaluated chips show only limited variation because they all came from a single manufacturing lot.
That observation is important when interpreting the demonstrated die-to-die lifetime differences: a larger multi-lot population could show greater variation than this experiment.
Technical Significance
The paper makes an important connection between three levels of reliability analysis:
- Physical degradation
- Externally measurable circuit behavior
- System lifetime
At the physical level, NBTI produces trapped charge and threshold-voltage shifts, while GOBD produces defects and resistive leakage paths.
At the observable level, both mechanisms alter ordinary transient VDD and ground signals.
At the system level, those extracted physical parameters feed statistical timing analysis and determine when a processor can no longer satisfy its operating-frequency requirement.
The method is therefore more informative than simply measuring a slowed output. It attempts to identify the underlying wearout parameters so that lifetime can subsequently be simulated under an arbitrary workload.
A second technical contribution is the explicit treatment of die-to-die calibration. Reliability parameters and process parameters are estimated separately for each chip, turning the lifetime model into a device-specific prediction rather than a generic technology-level forecast.
A third contribution is the separation of competing degradation mechanisms through carefully chosen stress conditions and iterative subtraction. The measurements do not require perfectly mechanism-specific electrical observables.
Industrial Impact
Source-supported implication: The proposed method is particularly useful for devices that were not originally designed with dedicated reliability monitors. It can extract aging information using external power and ground measurements, provided the design is available for detailed simulation and calibration.
Potential applications include:
- Reliability assessment of existing processor designs
- Screening chips according to expected lifetime
- Identification of unusually aging-sensitive dies
- Qualification of commercial or legacy components
- Remaining-useful-life estimation
- Failure-analysis support
- Reliability-aware frequency assignment
- Process monitoring through product-level measurements
Interpretation: A manufacturer could potentially use this approach to place chips into different reliability bins. A die with favorable calibrated NBTI, GOBD, and process parameters might be suitable for a high-performance operating point, while another chip could be assigned a lower frequency or a less demanding application.
For systems in which maintenance cost is high, periodic measurements could also support health monitoring without requiring dedicated degradation sensors—although the paper itself demonstrates calibration rather than a complete deployed prognostics system.
Why the Paper Matters
Most reliability methods treat aging as either a technology property or a property measured by a special sensor.
This paper shows a third possibility: aging information can be inferred from small changes in signals that already exist at the chip boundary.
That is important because reliability is inherently individualized. Two chips may have:
- Different initial transistor dimensions
- Different threshold voltages
- Different NBTI rates
- Different GOBD susceptibility
Applying the same generic lifetime estimate to both can therefore be unnecessarily pessimistic for one chip and unsafe for the other.
The work also highlights the importance of separating initial manufacturing variation from subsequent aging. Both influence timing, but they have different implications. Once both are calibrated, the remaining-lifetime prediction becomes considerably more constrained.
Limitations and Scope
The study has several important limitations.
- The fabricated test chips use 90-nm CMOS technology.
- Only NBTI and GOBD are included in the calibrated wearout framework.
- Positive BTI is excluded because it was not considered important for the 90-nm technology used.
- HCI is intentionally suppressed during the controlled NBTI stress experiment by using static inputs.
- The methodology assumes access to the circuit design and simulation models even though no embedded reliability monitor is required.
- Accurate measurements require high-resolution oscilloscope acquisition, averaging, and filtering.
- The evaluated population contains only nine chips.
- The chips come from one manufacturing lot, limiting observed die-to-die diversity.
- Each chip is experimentally stressed for only about 15,000 s; long-term lifetime is obtained through calibrated simulation rather than direct lifetime testing.
- Stress voltages up to approximately 2.7 V are far above the normal 1.2-V operating voltage and are used for accelerated characterization.
- The test vectors are described as arbitrarily chosen rather than optimized for parameter observability.
- The NBTI study uses controlled DC stress that does not represent normal application activity.
- The method requires different stress conditions and iterative fitting because NBTI and GOBD cannot be perfectly isolated physically.
- The GOBD model treats the locations and numbers of soft-breakdown paths statistically.
- There remains residual timing error from unmodeled parasitics and parameters even after process calibration.
- The lifetime simulator depends on the accuracy of the adopted physical wearout models.
- The paper does not demonstrate field monitoring over the full operational life of a deployed system.
- PBTI and self-heating are identified as future extensions for more scaled technologies.
These limitations mean that the paper primarily establishes the feasibility and methodology of chip-specific wearout calibration, rather than proving a universally applicable lifetime-monitoring solution for modern nanoscale processors.
Concise Technical Abstract
This paper presents a die-specific reliability calibration methodology for extracting negative bias temperature instability and gate-oxide breakdown parameters from transient power-supply and ground measurements without requiring embedded aging monitors. A trapping/detrapping model maps NBTI-induced oxide defects to threshold-voltage degradation, while a percolation and quantum-point-contact framework models GOBD-induced soft-breakdown paths and resistance. Full-chip simulations establish mappings between wearout state and shifts in the amplitude and timing of power/ground waveform extrema. Low-voltage stress conditions are used primarily for NBTI extraction and high-voltage conditions for GOBD, with iterative subtraction separating the remaining contributions of the competing mechanisms. The approach is experimentally demonstrated on nine 90-nm RISC microprocessors containing approximately 1.4 million transistors. High-resolution filtered waveform measurements recover chip-specific wearout parameters, which are incorporated into statistical critical-path analysis to estimate lifetime as a function of operating frequency. Additional extraction of die-specific nMOS/pMOS threshold voltages and channel lengths substantially reduces lifetime uncertainty associated with process variation. Calibrated simulations agree closely with measured path degradation under both NBTI- and GOBD-dominant stress conditions, demonstrating that ordinary VDD and ground signals can serve as external observables for chip-by-chip aging and remaining-lifetime estimation.
Linda Milor 
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