A Comprehensive Time-Dependent Dielectric Breakdown Lifetime Simulator for Both Traditional CMOS and FinFET Technology

Full citation: Yang, K., Liu, T., Zhang, R., and Milor, L. (2018). “A Comprehensive Time-Dependent Dielectric Breakdown Lifetime Simulator for Both Traditional CMOS and FinFET Technology.” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 26(11), 2470–2482. DOI: 10.1109/TVLSI.2018.2861769. 

Plain-Language Overview

As integrated circuits become smaller and denser, the insulating materials separating conductive structures become increasingly vulnerable to gradual electrical breakdown. Two relevant mechanisms are gate-oxide breakdown, which damages the dielectric inside a transistor, and middle-of-line time-dependent dielectric breakdown, which occurs between a transistor gate and a nearby contact.

This paper presents a lifetime simulator that evaluates both mechanisms at the level of standard cells and complete digital circuits. It supports conventional planar CMOS and FinFET technologies, whose layouts and vulnerable physical features differ substantially.

The simulator combines:

• Device-level lifetime models
• Transistor and layout geometry
• Circuit switching activity
• Cell input-state probabilities
• Voltage and temperature
• Die-to-die process variation
• Standard-cell composition
• Application and processor use scenarios

The authors demonstrate the method on an 8-bit fast Fourier transform circuit and a LEON3 microprocessor implemented using a traditional 90-nm CMOS process and a 15-nm FinFET design environment.

The central result is that gate-oxide breakdown remains the main modeled concern in the traditional CMOS examples, while middle-of-line TDDB becomes increasingly significant in the compact FinFET layouts. The paper carefully stops short of claiming that MOL TDDB universally dominates GOBD because the available MOL experimental data are limited.

What Problem the Paper Addresses

Circuit-level TDDB analysis is difficult because lifetime is not determined by technology parameters alone. A complete prediction must account for where vulnerable structures occur, how often they are electrically stressed, how hot each part of the circuit becomes, and how manufacturing variation changes critical dimensions.

Existing reliability studies had examined mechanisms such as:

• Bias temperature instability
• Hot-carrier injection
• Gate-oxide breakdown
• Back-end-of-line TDDB
• Electromigration
• Stress-induced voiding

According to the authors, previous work had not evaluated the effect of middle-of-line TDDB on a complete circuit or microprocessor.

MOL TDDB creates an additional challenge because it depends directly on physical layout. A netlist identifies transistors and their connections, but it does not fully describe the spacing and parallel overlap between a gate and an adjacent contact. The simulator therefore requires layout-analysis algorithms in addition to conventional netlist analysis.

The problem becomes more complex for FinFET technology because:

• The effective gate width depends on fin dimensions and fin count.
• The layer structure differs from planar CMOS.
• Layout shapes may be irregular polygons rather than simple rectangles.
• Multiple types of gate-to-contact vulnerable features may exist.
• Very small nominal spacing makes lifetime highly sensitive to alignment and dimensional errors.

The paper addresses these issues by developing separate feature-extraction methods for traditional CMOS and FinFET layouts and integrating them into a bottom-up circuit-lifetime workflow.

Questions the Paper Answers

The study addresses the following questions:

• How can gate-oxide and MOL TDDB vulnerability be extracted from digital circuit designs?
• Why do conventional CMOS and FinFET layouts require different extraction algorithms?
• How can transistor, gate, contact, and layout information be converted into standard-cell lifetime distributions?
• How should workload-derived state probabilities and temperature be incorporated into TDDB analysis?
• How can the lifetime distributions of individual features be combined into a full-circuit failure distribution?
• How strongly do input-state probabilities affect standard-cell TDDB lifetime?
• How do channel-length and gate-alignment variations alter GOBD and MOL TDDB lifetime?
• Which standard cells limit the lifetime of the FFT and LEON3 examples?
• Does a larger circuit necessarily have a shorter lifetime?
• How does technology scaling change the relative importance of GOBD and MOL TDDB?
• How sensitive are the mechanisms to voltage, temperature, and processor-use scenarios?

Key Technical Terms and Definitions

Time-Dependent Dielectric Breakdown

Time-dependent dielectric breakdown, or TDDB, is the progressive deterioration of an insulating material under sustained electrical and thermal stress. Defects accumulate until a conductive path forms through the dielectric.

Gate-Oxide Breakdown

Gate-oxide breakdown, or GOBD, occurs when a breakdown path forms through the dielectric between a transistor gate and the underlying channel or substrate.

This failure reduces the gate’s input resistance and impairs its ability to control transistor current.

The model used in the paper makes characteristic lifetime a function of:

• Device width and length
• Stress probability
• Gate voltage
• Temperature
• Weibull parameters
• Empirically fitted material and acceleration parameters

Middle-of-Line TDDB

Middle-of-line TDDB occurs between a gate structure and a nearby diffusion contact or active interconnect layer.

In traditional CMOS terminology, the relevant pair is described as the polysilicon control and contact pair. In the studied FinFET layout, the paper considers gate–AIL1 and GIL–AIL2 relationships.

The MOL model depends on:

• Parallel vulnerable length
• Spacing between adjacent structures
• Resulting electric field
• Temperature
• Stress probability
• Material-dependent parameters

Vulnerable Feature

A vulnerable feature is a physical dielectric region where the local geometry and electrical potential can lead to breakdown.

For GOBD, the vulnerable feature is associated with the transistor gate area. For MOL TDDB, it is the dielectric region between adjacent gate and contact structures.

Vulnerable Length

The vulnerable length, $L_i$, is the length over which two neighboring conductive structures run in parallel and expose the intervening dielectric to breakdown risk.

A longer vulnerable length contributes to a shorter modeled characteristic lifetime.

Line Space

Line space, $S_i$​, is the physical separation between the gate and contact structures.

Smaller spacing produces a larger electric field for the same applied voltage and can sharply reduce MOL TDDB lifetime.

Effective FinFET Width

A FinFET’s effective width is determined from the fin height and thickness:$$W_{\text{eff}}=T_{\text{fin}}+2H_{\text{fin}}$$

For a transistor containing multiple fins, this value is multiplied by the fin count.

This replaces the direct use of the drawn source/drain width employed for planar devices.

State Probability

State probability is the fraction of operating time that a node is at logic 0 or logic 1.

For a MOL feature located between two nets, stress occurs when the nets are at opposite logic levels. The paper computes the stress probability as:$$p_{\text{total}}=p_1(1-p_2)+p_2(1-p_1)$$

Characteristic Lifetime

The Weibull characteristic lifetime, $\eta$, is the time corresponding to approximately 63.2% cumulative failure.

Weibull Shape Parameter

The Weibull shape parameter, $\beta$, describes the slope and time dependence of the failure distribution.

The simulator combines the Weibull distributions of individual devices or vulnerable features to obtain cell- and circuit-level distributions.

Process Variation

The paper considers two primary die-to-die variations:

• Transistor channel-length variation
• Gate-location or gate-alignment offset

Channel-length variation affects GOBD and also changes MOL spacing. Gate offset specifically changes spacing asymmetrically: one side becomes wider while the opposite side becomes narrower.

Workflow

1. Select the circuit and technology library

The authors evaluate:

• An 8-bit FFT circuit
• A LEON3 microprocessor

Both are synthesized for:

• An IBM 90-nm traditional CMOS process
• The FreePDK15 FinFET process

The FinFET implementation uses the NanGate 15-nm Open Cell Library.

The number and types of standard cells differ between the traditional CMOS and FinFET libraries.

2. Extract GOBD transistor features

For traditional CMOS, transistor width and channel length are read from the standard-cell netlist.

For FinFET devices, the simulator calculates effective width from fin thickness, fin height, and the number of fins.

The extracted transistor information is stored for later lifetime calculation.

3. Extract traditional CMOS MOL features

The traditional CMOS method analyzes the relative geometry of polysilicon and contact rectangles.

A vulnerable feature is present only when a gate and contact overlap along one dimension while remaining separated in the other. The simulator distinguishes:

• No overlap
• Full overlap
• Partial overlap

Only neighboring structures are considered. More distant structures are excluded because intervening conductors shield their electric fields.

The algorithm groups connected polysilicon segments by electrical net, then calculates vulnerable length and spacing for each qualifying gate–contact pair.

4. Extract FinFET MOL features

FinFET layouts contain more layers and more complex geometries. The simulator must determine which GATE, GIL, AIL1, AIL2, via, and metal segments belong to the same net.

The extraction process uses:

• Rectangle-overlap testing
• Vertical connection analysis
• Point-in-polygon testing
• A ray-casting algorithm for irregular polygons
• Downward traversal through connected layout layers

The page 5 diagrams illustrate both the point-in-polygon problem and the two main forms of vertical layer connection handled by the extraction code.

5. Obtain workload activity

The circuit is synthesized on an FPGA, and monitors are placed at input/output interfaces to record:

• State probabilities
• Toggle rates

Synopsys PrimeTime propagates this information to internal nets.

For the FFT, the authors apply randomly generated inputs and operate the transform continuously.

For the LEON3, standard benchmarks are used to characterize operation. The study also considers use scenarios containing different proportions of:

• Active operation
• Standby
• Powered-off time

6. Calculate power and temperature

Net activity and layout RC information are used to determine power consumption.

COMSOL calculates the temperature distribution, including FinFET self-heating. Each standard cell is associated with a local temperature for lifetime calculation.

The thermal map on page 6 shows only a relatively small temperature spread across the modeled LEON3 because of the circuit’s limited physical size.

7. Calculate individual feature lifetimes

The simulator applies the GOBD model to each transistor and the MOL TDDB model to each extracted gate–contact feature.

Each feature’s lifetime depends on:

• Its geometry
• Its voltage
• Its temperature
• Its stress probability
• The relevant process parameters

8. Precharacterize standard cells

Individual feature distributions are combined to obtain a Weibull lifetime distribution for each standard cell.

The library is characterized across combinations of:

• Input-state probabilities
• Channel-length shifts
• Gate-offset shifts

For example, dividing each of three inputs into five probability ranges creates $5^3$53 input-state combinations. Adding seven channel-length categories and seven gate-offset categories greatly increases the number of MOL characterization cases.

This precharacterization is performed once. Circuit analysis can subsequently look up the appropriate lifetime distribution instead of recalculating every cell from its physical features.

9. Identify lifetime-limiting cells

The simulator compares the lifetime distributions of the standard-cell types used in each design.

It can identify:

• The cell type with the shortest characteristic lifetime
• The physical vulnerable features responsible for that limitation
• How lifetime varies with workload and process corner

10. Calculate complete-circuit lifetime

The lifetime distributions of all standard-cell instances are combined while preserving the relevant process-variation category and workload-dependent input states.

The process-corner distributions are then weighted according to the assumed normal distribution of channel length and gate offset.

Finally, the circuit failure probability is calculated with the Weibull relationship:$$P(t)=1-\exp [-{\left(\frac{t}{\eta }\right)}^{\beta }]$$

Main Findings

GOBD dominates the traditional CMOS examples

For the modeled traditional CMOS FFT and LEON3 circuits, GOBD produces shorter lifetime estimates than MOL TDDB.

The identified lifetime-limiting cells are:

• nor4_1× in the traditional CMOS FFT
• comp_42_1× in the traditional CMOS LEON3

The analysis therefore preserves the conventional importance of gate-oxide reliability in the older planar technology examples.

MOL TDDB becomes increasingly important in FinFET layouts

The FinFET layouts have much smaller conductor spacing and multiple potential MOL features. This makes MOL lifetime particularly sensitive to geometry.

The paper reports that voltage scaling reduces the modeled GOBD burden, while compact FinFET geometry decreases gate-to-contact separation and worsens MOL vulnerability.

The authors emphasize that this demonstrates an increasing concern, not definitive universal dominance. Their MOL model parameters are based on limited published experimental data.

Process variation affects FinFET MOL lifetime strongly

The most pronounced process sensitivity occurs when channel-length variation and gate-offset variation combine to reduce already small FinFET spacing.

The nominal minimum line space in the analyzed FinFET cells is 8 nm. A 30% dimensional change can reduce it to approximately 5 nm, and gate misalignment can decrease one side further.

This produces a substantial lifetime reduction in the adverse process corner.

By comparison:

• GOBD is affected by channel-length variation.
• Traditional CMOS MOL results are less sensitive to the modeled shifts.
• FinFET MOL TDDB is affected by both channel length and alignment.

Input-state probability has a comparatively small cell-level effect

The standard-cell curves for different input-state probabilities are relatively close.

The authors explain this using complementary transistor behavior:

• When an nMOS transistor is stressed, its complementary pMOS is generally not stressed.
• Logic 1 stresses dielectric paths to ground.
• Logic 0 stresses corresponding paths toward the supply.

For MOL features, opposite logic states on neighboring conductors determine stress, but changes in input probability still produce less variation than adverse physical spacing variation in the examples.

Process variation can make full-chip lifetime non-Weibull

Individual device and feature lifetimes are modeled with Weibull distributions. However, the complete population mixes Weibull distributions from different normally distributed process corners.

The resulting full-chip distribution is not exactly Weibull.

The adverse tails contain more early failures than a single fitted Weibull distribution would predict because they include samples from extreme dimensional and alignment conditions.

This finding is technically important because reliability estimates based on one nominal Weibull model could underrepresent early-life risk caused by process variation.

A smaller circuit can fail sooner than a larger circuit

Circuit size alone does not determine lifetime.

In traditional CMOS, the modeled FFT fails more slowly than the LEON3. In the FinFET case, the relationship reverses: the smaller FFT has the shorter lifetime.

The cause is the INV_X16 cell used in the FinFET FFT. It contains many vulnerable features and becomes the circuit’s lifetime-limiting cell.

The page 9 layout highlights the vulnerable regions within half of the symmetric INV_X16 cell. Its result illustrates that standard-cell composition and geometry can outweigh total cell count.

MOL TDDB is more sensitive to use scenarios

The LEON3 use-scenario analysis shows that MOL TDDB lifetime changes more across operating, standby, and off-time combinations than GOBD lifetime.

The authors explain the difference structurally:

• GOBD stress is associated primarily with one device gate voltage.
• MOL stress is determined by the relationship between two neighboring electrical nets.

Changes in system state can therefore alter MOL stress more strongly.

Different standard-cell types also respond differently to the same use-scenario change. This means application-aware cell selection could improve reliability.

GOBD and MOL TDDB respond differently to accelerated stress

The voltage–temperature results for two weeks of accelerated operation show that:

• GOBD is especially vulnerable to elevated voltage.
• MOL TDDB is especially likely at elevated temperature in the modeled conditions.

These distinct sensitivities could be used to guide accelerated testing or voltage-domain design.

The simulator can guide targeted redesign

Because the framework reports lifetime by cell type and physical feature, it can do more than generate one chip-level lifetime number.

A designer could use the output to:

• Replace a limiting cell with a more reliable cell combination
• Redraw a layout with greater gate-to-contact spacing
• Reduce the number or length of vulnerable features
• Select cells suited to a particular application profile
• Use multiple supply-voltage domains to reduce stress
• Compare reliability across process corners

Technical Significance

The paper provides a cross-layer path from device physics to circuit reliability:

1. Device-level TDDB equations describe the physical mechanisms.
2. Netlist and layout analysis identify vulnerable structures.
3. Workload emulation determines how often each structure is stressed.
4. Thermal analysis supplies local temperature.
5. Standard-cell precharacterization converts these factors into reusable lifetime models.
6. Statistical aggregation produces full-chip failure distributions.

A major contribution is the explicit treatment of MOL TDDB as a layout-dependent circuit mechanism. GOBD analysis can largely begin from transistor information in a netlist. MOL analysis requires geometric reasoning about adjacent structures, connected layers, polygons, spacing, and overlap.

The paper also introduces separate extraction logic for planar CMOS and FinFET designs. This is necessary because a simple extension of the planar algorithm would not capture the additional layers and feature types of the FinFET cell.

Another important contribution is the standard-cell precharacterization strategy. Although it requires many initial combinations of input states and process corners, it allows future circuit simulations to use library lookups. This makes the method more practical for architecture and design exploration.

Finally, the work demonstrates why reliability should not be reduced to transistor count. A particular cell layout can dominate a complete chip’s lifetime even when the chip is relatively small.

Industrial Impact

Source-supported implication: The simulator can identify standard cells and layout structures that dominate TDDB risk before a design is fabricated. This creates an opportunity to modify the cell library or replace vulnerable instances during design.

Potential applications include:

• Reliability-aware standard-cell library development
• Technology-node comparison
• FinFET layout qualification
• Application-specific lifetime assessment
• Process-corner reliability screening
• Multi-$V_{\text{DD}}$VDD​ design planning
• Identification of accelerated-test conditions
• Reliability-oriented cell replacement and synthesis

Interpretation: In an industrial design flow, the method could be connected to synthesis, place-and-route, activity analysis, power analysis, and signoff tools. A reliability constraint could then be treated similarly to timing or power constraints.

For example, a cell with acceptable delay and area might still be rejected because it contains too many short gate-to-contact spacings. A functionally equivalent combination of less vulnerable cells could be chosen instead.

The method could also help process and library teams prioritize specific geometries for silicon characterization. If simulations repeatedly identify one layout family as lifetime limiting, dedicated test structures could be created for those features.

Why the Paper Matters

Technology scaling does not merely increase the severity of existing failure mechanisms. It can change which physical structures matter most.

In traditional planar CMOS, gate-oxide breakdown is the familiar TDDB concern. In FinFET cells, reduced supply voltage helps gate-oxide lifetime, but tighter middle-of-line geometry creates a different risk between gates and contacts.

The paper shows that reliability analysis must therefore evolve with device architecture. A model that ignores layout-level MOL features may overlook the structures most sensitive to process misalignment in an advanced node.

It also shows that nominal geometry is not enough. Mixing dimensional variation with wearout distributions changes the tails of the complete lifetime distribution. Those tails are often the most important part of a high-reliability product assessment.

Most importantly, the simulator makes reliability actionable. Instead of reporting only a predicted chip lifetime, it points to the cell type and vulnerable layout features responsible for that lifetime.

Limitations and Scope

The paper has several important boundaries:

• Only GOBD and MOL TDDB are included in the simulator.
• Back-end-of-line TDDB is not analyzed.
• Other mechanisms such as BTI, HCI, electromigration, and stress-induced voiding are outside the model.
• The methodology is demonstrated with only an 8-bit FFT and a LEON3 microprocessor.
• Traditional CMOS results use an IBM 90-nm process, while FinFET results use FreePDK15 and an open NanGate library.
• Differences between the two technology libraries mean the comparison includes changes in both technology and available cell composition.
• The MOL lifetime parameters are derived from limited published experimental data.
• The authors explicitly state that the results indicate scaling trends but cannot establish that MOL TDDB is universally more important than GOBD.
• The standard-cell libraries contain substantially different numbers of cell types: the traditional CMOS library is much larger than the FinFET library used in the study.
• Process variation is modeled primarily as die-to-die channel-length and gate-offset variation.
• The assumed variation is normally distributed with a standard deviation equal to 10% of nominal.
• The characterization discretizes input probabilities and process shifts rather than treating every value continuously.
• The thermal variation in the modeled LEON3 is small; larger or more thermally heterogeneous chips may exhibit stronger spatial effects.
• The circuit activity is obtained through FPGA emulation and propagated using timing-analysis tools rather than measured from fabricated target-technology silicon.
• The complete lifetime results are simulation predictions rather than validation against full-chip TDDB failure measurements.
• Combining process-corner distributions produces a result that is not strictly Weibull, although Weibull equations remain central to the feature- and cell-level modeling.
• Only nearest-neighbor MOL features are extracted. More distant conductors are assumed to be shielded by intervening structures.
• The paper evaluates hard gate-oxide breakdown and does not present a detailed circuit-level treatment of progressive soft-breakdown behavior.
• The results depend on the adopted material constants, acceleration models, and assumed process distributions.

Concise Technical Abstract

This paper presents a circuit-level simulator for gate-oxide and middle-of-line time-dependent dielectric breakdown in traditional planar CMOS and FinFET technologies. GOBD features are extracted from transistor netlists, while MOL vulnerable features are obtained through technology-specific layout-analysis algorithms that calculate gate-to-contact spacing, parallel vulnerable length, and electrical connectivity. FinFET extraction incorporates effective fin width, multilayer connectivity, rectangle-overlap tests, and ray-casting point-in-polygon analysis. FPGA-derived activity profiles, PrimeTime state-probability propagation, layout-based power analysis, and COMSOL thermal simulation provide workload and temperature inputs. Device- and feature-level Weibull distributions are combined to precharacterize standard cells across input-state probabilities and die-to-die channel-length and gate-offset variations, then aggregated into full-circuit lifetime distributions. Experiments with an 8-bit FFT and LEON3 processor show GOBD-dominated behavior in the modeled traditional CMOS designs and increasing MOL TDDB importance in FinFET layouts. FinFET MOL lifetime is highly sensitive to combined dimensional and alignment errors, and mixed process-corner populations produce non-Weibull full-chip tails. The simulator identifies lifetime-limiting cells, including INV_X16 in the FinFET FFT, demonstrating that cell geometry can outweigh total circuit size. MOL TDDB is more sensitive than GOBD to processor-use scenarios, while accelerated-stress analysis shows stronger GOBD sensitivity to voltage and stronger MOL sensitivity to temperature.