Optimization of Experimental Designs for System-Level Accelerated Life Test in a Memory System Degraded by Time-Dependent Dielectric Breakdown

Full citation: Kim, D.-H., Hsu, S.-H., and Milor, L. (2019). “Optimization of Experimental Designs for System-Level Accelerated Life Test in a Memory System Degraded by Time-Dependent Dielectric Breakdown.” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 27(7), 1640–1650. DOI: 10.1109/TVLSI.2019.2909086. 

Plain-Language Overview

Electronic systems are normally qualified for long-term reliability by testing specially designed device structures at elevated voltage or temperature. The resulting failure data are used to predict how long complete circuits should operate under normal conditions.

That conventional approach has an important weakness: the failure of one transistor or interconnect does not always cause the entire circuit to fail. A processor or memory system may tolerate some physical defects because of its architecture, operating state, or built-in fault tolerance. Device-level testing alone therefore may not accurately represent system lifetime.

This paper proposes a method for designing accelerated life tests directly at the circuit or system level. The authors use the SRAM-based memory system of a LEON3 microprocessor as a case study and focus on three forms of time-dependent dielectric breakdown:

• Gate-oxide TDDB
• Middle-of-line TDDB
• Back-end-of-line TDDB

The method first identifies voltage and temperature regions in which failures from a target mechanism can be detected and separated as effectively as possible from competing mechanisms. It then selects test points and sample allocations that minimize uncertainty when accelerated-test results are extrapolated to normal operating conditions.

The study finds that the best designs in the examined test regions reduce to two test conditions. Gate-oxide breakdown is characterized through voltage acceleration, while middle- and back-end breakdown are characterized primarily through temperature acceleration.

What Problem the Paper Addresses

A conventional reliability qualification flow typically proceeds as follows:

1. Dedicated device structures are stressed under elevated conditions.
2. Failure times are fitted to statistical lifetime distributions.
3. Acceleration parameters are extracted.
4. Device reliability is projected to normal-use conditions.
5. Device qualification is treated as evidence that the complete system will be reliable.

The paper argues that this flow does not fully account for:

• Circuit-level tolerance to physical defects
• Differences in activity among memory cells
• The location of vulnerable features
• Interactions among multiple TDDB mechanisms
• The inability of ordinary electrical diagnosis to distinguish similar TDDB failures
• Statistical error caused by limited failures
• Extrapolation error between accelerated and normal conditions

The practical problem is not simply to apply the highest possible voltage or temperature. Excessive stress may accelerate the wrong mechanism, produce mixed failures, or create failure data that cannot be attributed accurately.

The authors therefore formulate accelerated-test planning as an optimization problem: determine where a target failure mechanism is detectable, where it is sufficiently selective relative to competing mechanisms, and which test points minimize lifetime-estimation error.

Questions the Paper Answers

The paper addresses the following questions:

• Why is device-level accelerated testing insufficient for estimating complete-system lifetime?
• Under which voltage and temperature conditions can each TDDB mechanism be observed in a memory system?
• How can a system-level test isolate TDDB mechanisms when their electrical symptoms are similar?
• How should detectability and mechanism selectivity define an acceptable test region?
• What statistical errors arise when Weibull lifetime parameters are estimated from accelerated-test data?
• How do limited sample size and mixed failure mechanisms affect the estimated characteristic lifetime?
• How should accelerated-test results be extrapolated to normal operating conditions?
• Are multivariable, multipoint test plans better than simpler plans?
• Which voltage or temperature points should be selected for GTDDB, MTDDB, and BTDDB?
• How many chips are required to achieve specified parameter-estimation accuracy?

Key Technical Terms and Definitions

Accelerated Life Test

An accelerated life test, or ALT, stresses a device or system at conditions more severe than normal operation so that failures occur within a practical testing period.

Voltage and temperature are the principal acceleration variables in this study.

Time-Dependent Dielectric Breakdown

Time-dependent dielectric breakdown, or TDDB, is the progressive degradation of an insulating material under electrical and thermal stress. Failure occurs when defects form a conductive path through the dielectric.

Gate-Oxide TDDB

Gate-oxide TDDB, abbreviated GTDDB, is breakdown of the dielectric between a transistor gate and its channel, source, or drain region.

In the paper’s SRAM models, potential GTDDB failures are represented as resistive shorts at several transistor-level locations.

Middle-of-Line TDDB

Middle-of-line TDDB, abbreviated MTDDB, occurs in the dielectric spacer between a transistor gate and a nearby contact.

Its lifetime depends on factors including gate-to-contact spacing, vulnerable length, electric field, temperature, and the probability that the feature is electrically stressed.

Back-End-of-Line TDDB

Back-end-of-line TDDB, abbreviated BTDDB, is dielectric breakdown between adjacent metal interconnects. It affects the low-k insulating material separating neighboring conducting lines.

Weibull Distribution

A Weibull distribution is used to represent failure time statistically. Its main parameters are:

• Characteristic lifetime, η: The time associated with approximately 63.2% cumulative failure.
• Shape parameter, β: The slope of the lifetime distribution on a Weibull plot and an indicator of how failures evolve with time.

Acceleration Factor

An acceleration factor relates lifetime under elevated stress to lifetime under normal operating conditions.

For BTDDB and MTDDB, the paper uses an electric-field and Arrhenius temperature relationship. GTDDB is modeled with a separate voltage- and temperature-dependent lifetime equation.

Detectability

Detectability means that enough failures from a mechanism occur during the limited test period to support statistical estimation.

The authors define a lower probability-of-failure bound from:

• The minimum number of failures that must be detected
• The number of SRAM cells available in the memory system

A test condition is unacceptable when too few relevant failures occur.

Acceptability Region

An acceptability region is the set of accelerated voltage and temperature conditions where the target failure mechanism is detectable.

The region is subsequently refined by considering selectivity and estimation error.

Selectivity

Selectivity is defined as the failure probability of the target mechanism divided by the total failure probability from all considered TDDB mechanisms:$${\text{Selectivity}}_i=\frac{F_i}{\sum _j{F}_j}$$A selectivity approaching one indicates that failures at the condition are dominated by the target mechanism.

Built-In Self-Test

Built-in self-test, or BIST, is on-chip test logic used to detect memory failures.

The memoryless BIST approach referenced in the paper can separate TDDB failures from some other failure categories, but it cannot reliably distinguish GTDDB, MTDDB, and BTDDB from one another. The proposed test design compensates for this limitation by selecting mechanism-specific stress conditions.

Generalized Maximum-Likelihood Estimation

The authors use a generalized maximum-likelihood estimator to extract Weibull characteristic lifetime and shape parameters from time-to-failure samples.

The accuracy of the estimates improves as the number of observed failures increases.

Area Scaling

Area scaling estimates the Weibull shape parameter by comparing characteristic lifetimes from groups with different effective areas.

For a memory array, cells must be grouped so that the first failing cell determines the group’s time to failure.

Wilson Interval

The Wilson interval is a confidence interval for a binomial proportion. The paper uses it to quantify uncertainty in mechanism selectivity and propagate that uncertainty into the characteristic-lifetime estimate.

Design of Experiments

Design of experiments, or DoE, refers to the structured choice of:

• Number of test conditions
• Voltage and temperature settings
• Distance between test settings
• Number of chips assigned to each condition

The optimization objective is to minimize uncertainty in lifetime at normal operating conditions.

Workflow

1. Begin with calibrated device-level TDDB models

The methodology uses physical lifetime models for GTDDB, MTDDB, and BTDDB. Model parameters are calibrated with empirical data from earlier device-level studies.

GTDDB lifetime depends on transistor dimensions, gate voltage, temperature, and stress probability. MTDDB and BTDDB depend on vulnerable dielectric length, spacing, electric field, temperature, and activity.

2. Model TDDB defects within an SRAM cell

Potential dielectric-breakdown paths are represented as resistive shorts between conducting nodes.

The paper identifies:

• Eight modeled GTDDB locations
• Eight modeled MTDDB locations
• Nine modeled BTDDB locations

Figures 4 and 5 connect these electrical short models to potential defect locations in the SRAM schematic and physical layout.

3. Propagate lifetime from features to the memory system

The analysis follows a bottom-up process:

1. Estimate the lifetime of every vulnerable location.
2. Combine feature distributions into SRAM-cell lifetime distributions.
3. Combine cells into individual memory-block distributions.
4. Combine the memory blocks into a complete memory-system lifetime distribution.

The LEON3 case study includes approximately 226,000 SRAM cells distributed across blocks such as:

• Instruction and data RAM
• Instruction and data caches
• Instruction and data translation lookaside buffers
• Register file

The SRAM implementation uses a 28-nm process design kit. 

4. Simulate accelerated-test failure statistics

The authors simulate memory failure probability over a grid of voltage and temperature conditions. The principal acceptability-region analysis assumes a 14-day test.

The resulting statistics indicate which mechanisms would produce observable failures under each stress combination.

5. Apply a detectability requirement

A condition must produce at least a specified minimum number of failures before it can be used to estimate a lifetime distribution.

Because the modeled memory contains 231,424 SRAM cells, a minimum failure count can be translated into a minimum cumulative failure probability.

This criterion produces an initial acceptability region for each mechanism.

6. Calculate mechanism selectivity

Within each detectable region, the authors calculate the fraction of all TDDB failures attributable to the target mechanism.

The selectivity maps show that:

• GTDDB can dominate under sufficiently high-voltage conditions.
• MTDDB can dominate in a lower-voltage, temperature-accelerated region.
• BTDDB has no region in which its selectivity reaches one.

The paper therefore concludes that BTDDB is intrinsically more difficult to isolate in the studied memory system. 

7. Estimate errors at accelerated conditions

Two principal error sources are evaluated:

• Sampling error: Uncertainty caused by the finite number of observed failures.
• Selectivity error: Uncertainty caused by some detected TDDB failures originating from mechanisms other than the target.

These errors vary across the voltage–temperature domain. A condition with high acceleration may generate many failures but have poor selectivity. Another condition may have excellent selectivity but too few failures.

The two uncorrelated error components are combined by a root-sum-of-squares calculation.

8. Estimate errors at normal operating conditions

The Weibull parameters obtained at accelerated conditions must be extrapolated to the normal condition.

Regression error depends on:

• Number of test conditions
• Distance between those conditions
• Their distance from the normal operating point
• Estimation error at each accelerated condition
• Number of chips assigned to the conditions

The study evaluates voltage steps of 0.1–0.5 V, temperature steps of 5–25 °C, and designs containing two to five nominal test points.

9. Optimize the test configuration

The authors compare one-dimensional plans with L-, T-, X-, and factorial-style plans in the voltage–temperature space.

Although adding points can reduce regression error in an idealized equal-error case, the actual error surface is uneven because sample availability and selectivity change with stress.

When total sample size is held constant, the best designs place samples at two extreme conditions and accelerate only one variable.

10. Optimize sample allocation

After selecting two conditions, the fraction of chips at each point is optimized.

The optimum low-point fractions are reported as:

• 58% for GTDDB
• 66% for MTDDB
• 32% for BTDDB

The unequal BTDDB allocation reflects its different error and selectivity behavior.

Main Findings

System-level testing complements rather than replaces device testing

The proposed framework still relies on physical models calibrated from device-level data. Its purpose is to add circuit architecture, activity, and tolerance information that dedicated device structures do not contain.

The system-level test estimates the failure behavior of the actual memory organization instead of assuming that every device breakdown immediately produces system failure.

Detectability alone is insufficient

A test condition may generate measurable failures but still be poor for characterizing a specific mechanism.

For example, several TDDB mechanisms may fail together at high stress. The resulting sample count would be large, but the source of each failure would be uncertain.

The paper therefore requires both:

• Sufficient failure detection
• High target-mechanism selectivity

GTDDB is best characterized with voltage acceleration

The optimized GTDDB test uses:

• 2.3 V at nominal temperature
• 3.0 V at nominal temperature

The more precise allocation assigns approximately 58% of chips to the lower-voltage condition.

For a reported 10% standard-deviation target, the paper assigns:

• 60 chips at 2.3 V
• 43 chips at 3.0 V

For a 20% target:

• 15 chips at 2.3 V
• 11 chips at 3.0 V

The strong voltage dependence of GTDDB makes a voltage-only test more informative than a combined voltage–temperature plan.

MTDDB is best characterized with temperature acceleration

The optimized MTDDB conditions are:

• 70 °C at nominal voltage
• 150 °C at nominal voltage

Approximately 66% of chips are assigned to the lower-temperature point.

For a 10% standard-deviation target:

• 36 chips at 70 °C
• 18 chips at 150 °C

For a 20% target:

• 9 chips at 70 °C
• 5 chips at 150 °C

MTDDB requires fewer chips than the other mechanisms under the modeled assumptions because the selected region combines useful failure counts with comparatively strong selectivity.

BTDDB is difficult to isolate

The optimized BTDDB conditions are:

• 110 °C at nominal voltage
• 150 °C at nominal voltage

Only about 32% of samples are placed at the lower-temperature condition, meaning most samples are assigned to 150 °C.

For a 10% standard-deviation target, the reported allocation is:

• 578 chips at 110 °C
• 1,227 chips at 150 °C

For a 20% target:

• 145 chips at 110 °C
• 307 chips at 150 °C

The much larger requirement follows from BTDDB’s poor selectivity. The paper’s selectivity map contains no stress condition where BTDDB completely dominates GTDDB and MTDDB.

The extracted text separately reports BTDDB totals of 1,839 chips for the 10% target and 460 chips for the 20% target, while the later per-condition allocations sum to 1,805 and 452, respectively. The source does not reconcile this numerical discrepancy. 

The optimum is effectively a two-point design

The authors compare plans described as having two to five points. During optimization, additional samples move to one of the two extreme vertices rather than remaining at intermediate conditions.

The resulting experiment therefore contains only two distinct stress settings. Intermediate points do not provide enough additional regression value to justify dividing the fixed sample population among them.

Only one acceleration variable should be changed

The evaluated L-, T-, X-, and factorial designs vary both voltage and temperature. However, the lowest errors are obtained when one parameter remains nominal.

This produces:

• Voltage-only acceleration for GTDDB
• Temperature-only acceleration for MTDDB
• Temperature-only acceleration for BTDDB

This reduces extrapolation complexity and places samples in regions where the target mechanism is more effectively isolated.

Test points should be separated, but not chosen from error maps alone

Standard regression theory favors test conditions that are far apart because wider separation improves estimation of the acceleration relationship.

At the same time, test points should ideally remain close to the normal operating condition to reduce extrapolation distance.

The actual optimum balances both objectives against:

• Number of failures
• Mechanism selectivity
• Feasible test boundaries
• Uneven estimation error across the domain

The farthest mathematically possible points are therefore not automatically the best experimental points.

Technical Significance

The paper’s principal contribution is a mechanism-aware statistical framework for designing system-level accelerated life tests.

It links four types of analysis that are often treated separately:

1. Physical TDDB lifetime modeling
2. Circuit- and system-level failure simulation
3. Statistical uncertainty in Weibull parameter extraction
4. Optimization of accelerated-test conditions

A particularly important contribution is the explicit modeling of imperfect failure attribution. The framework does not assume that BIST or post-failure analysis can identify the exact TDDB mechanism. Instead, it treats selectivity as a measurable probability and propagates its uncertainty into the lifetime estimate.

The work also shows that sample size in a memory ALT can be interpreted in two ways:

• The number of failing cells used to estimate a distribution
• The number of chips needed to obtain the required system-level accuracy

Because one memory contains many cells, large feature-level failure samples can be produced. However, when poor selectivity dominates—as with BTDDB—many complete chips may still be required.

The optimal-design analysis further demonstrates that a visually comprehensive voltage–temperature experiment is not necessarily statistically efficient. Under a fixed sample budget, concentrating samples at two carefully chosen conditions can outperform a multipoint factorial design.

Industrial Impact

Source-supported implication: The proposed method can reduce the trial-and-error process used to select system-level accelerated-test conditions. It provides a simulation-based procedure for screening conditions before physical test hardware and large chip populations are committed.

Potential industrial uses include:

• Product-level SRAM qualification
• Processor-memory reliability planning
• Selection of mechanism-specific burn-in conditions
• Estimation of required qualification sample sizes
• Planning of BIST-enabled lifetime experiments
• Comparison of process technologies or memory organizations
• Investigation of unexpectedly mixed failure populations

Interpretation: The methodology could reduce qualification time and cost when the target mechanism has a well-defined, high-selectivity test region. The MTDDB example is especially favorable because relatively few chips are required under the paper’s assumptions.

The BTDDB result also has practical value even though it is unfavorable. It warns engineers that a proposed system-level test may be economically impractical because no stress condition isolates the mechanism adequately. In that situation, dedicated structures, stronger diagnosis, or a different experiment may be preferable.

Why the Paper Matters

Accelerated testing is often treated as a straightforward choice of high voltage and high temperature. This paper demonstrates that the most aggressive test is not necessarily the most informative test.

A useful system-level ALT must simultaneously answer three questions:

• Will enough failures occur?
• Will those failures primarily come from the mechanism being studied?
• Will the resulting data predict lifetime at normal conditions accurately?

Ignoring any one of these can lead to a misleading qualification result.

The work also highlights an important distinction between physical reliability and functional reliability. A memory system can contain physical defects without immediately becoming unusable. Conversely, the accumulation and location of defects may create a system failure that is not predicted accurately by treating every device in isolation.

By incorporating memory architecture and competing mechanisms into experimental design, the paper moves reliability assessment closer to the behavior of the manufactured product.

Limitations and Scope

The paper’s results are bounded by the following assumptions and study choices:

• The case study covers one LEON3 memory system implemented with a 28-nm PDK.
• Approximately 226,000 SRAM cells are modeled; other memory capacities will change detectability and sample requirements.
• The acceptability-region analysis assumes a 14-day accelerated test.
• Only GTDDB, MTDDB, and BTDDB are included.
• The authors explicitly exclude other SRAM degradation mechanisms such as bias temperature instability, hot-carrier injection, electromigration, and stress migration.
• Failure statistics are generated through system-level reliability simulation rather than a reported physical campaign using the optimized chip counts.
• Device models are calibrated from prior empirical studies, so prediction quality depends on those models and parameters.
• TDDB faults are represented as resistive shorts at predefined potential defect locations.
• The method assumes BIST can detect TDDB-related memory failures but cannot identify the exact TDDB subtype.
• The usefulness of selectivity depends on the assumption that the considered TDDB mechanisms account for the relevant TDDB failure population.
• Weibull distributions and the selected acceleration equations define the statistical and physical forecasting framework.
• Process variation is included in the error analysis, but the available text does not establish that all manufacturing or spatial-variation effects are represented.
• The reported optimal points are specific to the modeled process, circuit, normal operating condition, test duration, and error objective.
• The optimization examines a defined family of two- to five-point voltage–temperature plans. It does not prove that the resulting design is globally optimal among every possible sequential or adaptive test strategy.
• The extracted source contains a discrepancy between the stated total BTDDB chip requirements and the sums of the later per-condition allocations.

The authors state that the methodology can be extended to other SRAM failure mechanisms, other circuit types, FinFET systems, and three-dimensional integrated circuits. 

Concise Technical Abstract

This paper proposes a simulation-driven methodology for optimizing system-level accelerated life tests of SRAM memory affected by gate-oxide, middle-of-line, and back-end-of-line time-dependent dielectric breakdown. Device-level lifetime models are propagated through resistive defect models, SRAM-cell distributions, memory blocks, and the complete LEON3 memory system. Simulated failure statistics over voltage and temperature define mechanism-specific acceptability regions based on minimum failure detectability and selectivity relative to competing TDDB mechanisms. Weibull characteristic-lifetime and shape-parameter errors are evaluated using generalized maximum-likelihood estimation, area scaling, binomial selectivity modeling, Wilson confidence intervals, and regression to normal-use conditions. Comparison of two- to five-point designs shows that the optimized plans collapse to two distinct stress settings with one accelerated variable. The reported conditions are 2.3 and 3.0 V at nominal temperature for GTDDB, 70 and 150 °C at nominal voltage for MTDDB, and 110 and 150 °C at nominal voltage for BTDDB. MTDDB requires the smallest test population, while BTDDB requires substantially more chips because no modeled condition provides complete mechanism selectivity. The framework provides a systematic alternative to ad hoc selection of circuit- and system-level reliability-test conditions.