Full citation: Wu, Y.-D., Yang, K., Hsu, S.-H., and Milor, L. (2020). “Optimal Accelerated Test Framework for Time-Dependent Dielectric Breakdown Lifetime Parameter Estimation.” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 28(12), 2658–2670. DOI: 10.1109/TVLSI.2020.3017950.
Plain-Language Overview
Modern integrated circuits are expected to operate reliably for many years, but waiting for devices to fail under normal conditions is impractical. Engineers therefore test circuits at elevated voltages and temperatures, where physical degradation occurs more quickly, and use the resulting data to predict lifetime under normal operating conditions.
The difficulty is that different test conditions may accelerate different failure mechanisms. A test performed at very high voltage, for example, may mainly trigger gate-oxide breakdown, while a high-temperature test may emphasize dielectric breakdown between a transistor gate and a nearby contact. If several mechanisms compete during the same experiment, it becomes difficult to determine which mechanism caused each failure and to estimate its lifetime model accurately.
This paper presents a simulation-based framework for choosing accelerated-test regions, specific test conditions, and sample sizes for two time-dependent dielectric breakdown mechanisms:
- Gate-oxide breakdown
- Middle-of-line time-dependent dielectric breakdown
The authors demonstrate the framework using an 8-bit fast Fourier transform circuit and a Leon3 microprocessor. Their central finding is that the two mechanisms should generally be tested separately: gate-oxide breakdown is best isolated through voltage acceleration, while middle-of-line breakdown is best isolated through temperature acceleration.
What Problem the Paper Addresses
Circuit qualification traditionally relies heavily on acceleration factors obtained from dedicated device-level test structures. Those factors may not fully represent complete digital circuits, where thousands of differently stressed transistors and layout features contribute to system failure.
The paper addresses several related problems:
- Competing failure mechanisms: The same accelerated-test condition may produce failures from more than one degradation process.
- Limited test duration: Samples that fail too slowly provide no useful failure observation within the test period, while samples that fail immediately may also be unsuitable for parameter estimation.
- Statistical uncertainty: Weibull lifetime parameters estimated from a limited number of failures contain sampling error.
- Extrapolation error: Lifetime estimates obtained at elevated voltage or temperature must be projected back to normal operating conditions.
- Circuit dependence: Suitable test conditions may change with circuit size, cell composition, workload, and manufacturing variation.
The framework is intended to identify conditions that provide enough observable failures, maintain high selectivity for the target mechanism, and minimize uncertainty in the predicted lifetime at use conditions.
Questions the Paper Answers
The study investigates the following questions:
- Which voltage and temperature combinations are suitable for isolating gate-oxide breakdown and middle-of-line dielectric breakdown?
- How should vulnerable transistor and layout features be combined to estimate complete-circuit lifetime?
- How do limited sample size and uncertain failure attribution affect Weibull parameter estimates?
- Which accelerated-test points minimize prediction error at normal operating conditions?
- How should test samples be allocated between high- and low-stress test points?
- How do circuit size, circuit type, workload, and process variation change the optimal test plan?
- How many samples are required to meet a specified confidence or error target?
Key Technical Terms and Definitions
Time-Dependent Dielectric Breakdown
Time-dependent dielectric breakdown, or TDDB, is the gradual deterioration of an insulating material under sustained electric-field and thermal stress. Failure occurs when defects accumulate sufficiently to create a conductive path through the dielectric.
Gate-Oxide Breakdown
Gate-oxide breakdown, abbreviated GOBD, occurs when a conductive path forms through the thin dielectric between a transistor gate and its channel or substrate. The resulting failure reduces gate resistance and interferes with the transistor’s ability to control current.
In the model used by the authors, GOBD lifetime depends on factors including gate voltage, temperature, transistor dimensions, oxide properties, and the fraction of time the device is electrically stressed.
Middle-of-Line TDDB
Middle-of-line TDDB, or MOL TDDB, occurs in the dielectric separating a transistor gate from an adjacent contact or active interconnect feature. It has become increasingly important as gate-to-contact spacing has decreased in advanced technology nodes.
Its lifetime is especially sensitive to:
- Gate-to-contact spacing
- Parallel vulnerable length
- Electric field
- Temperature
- Gate/contact alignment error
Vulnerable Feature
A vulnerable feature is a circuit location where an applied electric field can progressively damage the surrounding dielectric.
For GOBD, the vulnerable feature is the transistor gate area. For MOL TDDB, it is the dielectric region between a gate and a nearby contact.
Weibull Distribution
The authors model failure time with a two-parameter Weibull distribution:
- Characteristic lifetime, η: The time at which approximately 63.2% of the population is predicted to have failed.
- Shape parameter, β: A parameter describing how rapidly the failure rate changes with time.
The circuit-level Weibull distribution is constructed by combining the lifetime distributions of its devices, vulnerable features, standard cells, and complete set of cell instances.
Duty Cycle
Duty cycle is the fraction of operating time during which a circuit node remains at a particular logic level. It determines how often a transistor or dielectric feature experiences electrical stress.
Selectivity
Selectivity is the probability that an observed circuit failure was caused by the target wearout mechanism rather than a competing mechanism.
High selectivity makes the measured failure data easier to attribute and reduces uncertainty in the estimated lifetime parameters.
Feasible or Optimal Test Region
The feasible test region is the set of voltage–temperature combinations where:
- A useful number of samples fail during the test period.
- Samples do not fail too quickly.
- The target mechanism has adequate selectivity.
- The resulting Weibull parameters can be estimated with acceptable error.
The authors define their optimal region as conditions where the total estimation error is less than twice the global minimum error for the mechanism under consideration.
Workflow
1. Extract vulnerable physical features
The simulator analyzes the circuit netlist to obtain transistor dimensions for GOBD modeling. It analyzes standard-cell layouts to identify neighboring gate–contact pairs, their spacing, and their parallel vulnerable lengths for MOL TDDB modeling.
2. Determine circuit operating activity
The FFT and Leon3 designs are emulated on an FPGA to obtain realistic activity information. Synopsys PrimeTime is then used to propagate duty-cycle information to internal circuit nets.
For the Leon3, the analysis includes operating, standby, and powered-off modes under several use scenarios.
3. Calculate feature-level lifetime distributions
The framework applies physical lifetime models to each transistor or gate–contact feature using its geometry, voltage, temperature, and stress probability.
For a MOL feature, stress occurs when the gate and contact are at opposite logic levels.
4. Construct standard-cell lifetime models
The individual feature distributions are combined to estimate the Weibull characteristic lifetime and shape parameter for each standard cell.
Cells are pre-characterized for different input duty-cycle combinations so that an appropriate lifetime distribution can be assigned when a circuit workload is known.
5. Construct the complete-circuit lifetime distribution
The lifetime distributions of all standard-cell instances are combined. This calculation accounts for both the number of cells and their types, layouts, and switching activities.
6. Evaluate accelerated-test conditions
The authors simulate tests over a range of voltages and temperatures. At each point, they calculate how many samples are expected to fail between a lower screening time and the maximum test duration.
The primary example assumes:
- 100 tested samples
- A two-week maximum test duration
- A one-second lower time limit
7. Calculate estimation error
Two error components are combined:
- Sample-size error: Uncertainty in the Weibull parameters caused by the limited number of observed failures.
- Selectivity error: Uncertainty caused by failures from a competing wearout mechanism.
Conditions with too few usable failures or poor mechanism selectivity are excluded.
8. Optimize the experimental design
Within the feasible region, weighted regression is used to select test points that minimize the variance of the lifetime estimate at normal operating conditions.
The framework also optimizes how the total sample population should be divided among the selected test points.
Main Findings
Different mechanisms require different acceleration strategies
The simulations show a clear separation between the preferred conditions for the two mechanisms:
- GOBD is primarily accelerated by voltage.
- MOL TDDB is more strongly isolated through temperature acceleration at relatively low voltage.
This distinction is important because testing both mechanisms under the same aggressive condition could obscure the cause of failure.
Two-point experiments perform best for the studied test regions
After evaluating designs containing two to five test points, the authors report that the best plans for the studied domains use only two points. The points are placed along an axis so that only one stress variable is accelerated:
- Voltage is varied for GOBD while temperature remains at its nominal value.
- Temperature is varied for MOL TDDB while voltage remains at its nominal value.
Keeping one parameter unaccelerated reduces the extrapolation distance and therefore lowers prediction uncertainty at use conditions.
Unequal sample allocation improves efficiency
Equal allocation between the two test points is not always optimal.
For GOBD, the improvement from unequal allocation is modest. For the FFT circuit, the optimized voltage points shift slightly to approximately 1.08 and 1.28 V, with about 60% of the samples assigned to the lower-voltage point. The resulting reduction in standard deviation is approximately 1%.
For MOL TDDB, unequal allocation is more beneficial:
- The FFT test points change from approximately 465 and 600 K to 450 and 600 K, with about 80% of samples at the lower temperature.
- The Leon3 test points change from approximately 470 and 600 K to 460 and 600 K, with about 75% of samples at the lower temperature.
The reported standard-deviation improvements are approximately 11% for the FFT and 12% for the Leon3.
MOL TDDB is harder to estimate precisely
The confidence bounds obtained for GOBD are considerably tighter than those for MOL TDDB. The paper’s sample-size analysis also shows that more samples are generally required to achieve the same target uncertainty for MOL TDDB.
The authors attribute this partly to the smaller effective separation between feasible MOL temperature test points and the larger uncertainty associated with mechanism selectivity.
Circuit composition matters, not only circuit size
The FFT contains fewer standard cells than the Leon3, yet it has a shorter simulated lifetime. Its vulnerability is linked to frequent use of the FA_X1 full-adder cell, which has more GOBD and MOL TDDB vulnerable features than a frequently used Leon3 cell such as AOI22_X1.
Thus, lifetime cannot be predicted from total gate or cell count alone. Cell type, layout geometry, and workload must also be considered.
Increasing circuit size changes the feasible regions
When the circuits are replicated to model systems ten and one hundred times larger:
- The feasible MOL TDDB region expands.
- The GOBD region becomes narrower.
The expansion occurs because additional MOL vulnerable features reduce MOL lifetime and improve its selectivity over part of the voltage range. At the same time, larger circuits fail more rapidly at highly accelerated GOBD conditions, reducing the number of usable samples and narrowing the GOBD test domain.
Workload scenarios have limited influence in the studied Leon3 cases
The authors analyze several Leon3 usage profiles with different proportions of operating, standby, and powered-off time. The simulated GOBD and MOL TDDB lifetimes are similar across these scenarios, so the corresponding optimal test regions change little.
This is a result for the workloads and designs studied and should not be interpreted as evidence that workload is unimportant for all circuits.
Process variation affects MOL testing more strongly
A ±30% channel-length variation produces only small changes in the optimal GOBD test plan.
MOL TDDB is more sensitive because channel-length and gate-alignment variations directly modify gate-to-contact spacing. Some process corners therefore require adjusted temperature points to remain inside the feasible test region.
The authors recommend using a test plan derived from nominal process parameters when possible, with small modifications when a nominal point becomes infeasible at a process corner.
Technical Significance
The paper connects physical dielectric-breakdown models with circuit activity, cell layouts, Weibull statistics, and design-of-experiments optimization.
Its main technical contribution is not a new TDDB physics model. Instead, it provides a systematic method for converting existing device-level lifetime models into a circuit-level accelerated-test plan.
The framework improves on a qualification approach that assumes a fixed acceleration factor. It estimates both the lifetime at use conditions and the acceleration relationship from multiple circuit-level test conditions.
The treatment of selectivity is particularly important. By representing failure attribution as a source of statistical uncertainty, the method recognizes that a complete circuit can fail through multiple competing wearout processes even when the experiment is intended to characterize only one.
Industrial Impact
Source-supported implication: The framework can help reliability engineers select stress conditions before manufacturing and testing large numbers of circuit samples. Simulation can eliminate conditions that would produce too few failures, immediate failures, or poor separation between mechanisms.
Interpretation: In industrial qualification programs, this approach could reduce test cost and calendar time by concentrating samples at statistically informative conditions. It could also improve diagnosis when product-level accelerated tests disagree with predictions derived from device test structures.
Potential applications include:
- Advanced CMOS and FinFET reliability qualification
- Automotive and long-lifetime electronics
- Process-development comparisons
- Standard-cell library reliability characterization
- Reliability-aware system and product design
- Planning of circuit-level failure-analysis experiments
The framework is especially relevant as MOL structures become more vulnerable to small spacing and alignment variations in highly scaled processes.
Why the Paper Matters
Accelerated testing is useful only when the accelerated failures remain informative about normal operation. Applying excessive voltage or temperature without considering competing mechanisms can produce a large quantity of failure data that does not accurately identify the intended lifetime model.
This paper shows that test planning should jointly consider:
- Physical acceleration behavior
- Circuit layout and switching activity
- Number of observable failures
- Competing failure mechanisms
- Statistical parameter uncertainty
- Extrapolation to use conditions
- Process variation
Its broader message is that circuit reliability qualification should be treated as an optimization problem rather than as the application of a single conventional stress condition.
Limitations and Scope
The authors identify or imply several boundaries to the study:
- Only GOBD and MOL TDDB are included in the competing-mechanism analysis.
- BEOL TDDB, bias-temperature instability, hot-carrier injection, electromigration, and stress-induced voiding are not modeled in the proposed test optimization.
- Results are demonstrated with only two digital designs: an 8-bit FFT circuit and a Leon3 microprocessor.
- The designs use the Nangate open-cell library and FreePDK15 process assumptions. The library contains a relatively limited variety of standard-cell types.
- Circuit failures and lifetime observations are generated through reliability simulation rather than reported silicon-level circuit qualification experiments.
- Two-parameter Weibull distributions are assumed for the modeled wearout mechanisms.
- The method relies on device-level physical models and parameters previously derived from dedicated test structures.
- Process variation is represented mainly through die-to-die channel-length and gate-alignment shifts.
- Line-edge roughness is neglected because the authors consider it smaller than the modeled die-to-die variation.
- The approximation that devices within a standard cell experience the same parameter shift may not fully capture spatially complex within-die variation.
- The specific optimal voltages, temperatures, and sample allocations are technology-, circuit-, model-, and test-duration-dependent. They should not be transferred directly to another product without recalculation.
The paper proposes extending future work to additional front-end, middle-of-line, and back-end wearout mechanisms.
Concise Technical Abstract
This paper presents a simulation-driven design-of-experiments framework for estimating circuit-level Weibull lifetime parameters for gate-oxide breakdown and middle-of-line time-dependent dielectric breakdown. Device and layout vulnerable features are extracted, combined with workload-dependent stress probabilities, and aggregated from feature level to standard-cell and full-circuit lifetime distributions. Feasible accelerated-test regions are identified by combining Weibull sampling uncertainty with error caused by imperfect selectivity between competing failure mechanisms. Weighted regression is then used to select test points and sample allocations that minimize lifetime-prediction variance at use conditions. Studies of an 8-bit FFT circuit and a Leon3 microprocessor indicate that GOBD is most effectively characterized through voltage acceleration, whereas MOL TDDB is most effectively characterized through temperature acceleration. For the analyzed regions, optimized two-point designs outperform more complex arrangements, and unequal sample allocation provides its largest benefit for MOL TDDB. Circuit composition, circuit size, and process variation affect the feasible test regions, while the analyzed Leon3 use scenarios have comparatively little effect.
Linda Milor 
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