A BIST Circuit for DLL Fault Detection

Full citation: Cheng Jia and Linda Milor, “A BIST Circuit for DLL Fault Detection,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 16, no. 12, pp. 1687–1695, December 2008. DOI: 10.1109/TVLSI.2008.2001732. 

Plain-Language Overview

Delay-locked loops (DLLs) are timing circuits used to align clock signals inside high-speed integrated circuits. Because DLLs are often buried inside much larger chips, directly testing them can be difficult: their internal signals may not be externally accessible, and adding conventional test circuitry can disturb the very timing behavior being measured.

Jia and Milor propose a compact built-in self-test (BIST) circuit that determines whether a DLL has successfully achieved phase lock. Rather than measuring detailed performance specifications with precision instrumentation, the proposed circuit asks a simpler manufacturing-test question: Is the DLL behaving closely enough to a properly locked DLL, or is there evidence of a fault?

The BIST compares the DLL reference clock with its output clock using an XNOR gate. If the two clocks are properly aligned, the XNOR output remains high except for small glitches caused by normal static phase error and jitter. The BIST samples those glitches at carefully selected times using uncalibrated delay lines. Large phase errors, failure to lock, or stuck outputs can therefore generate a digital fail result.

The method requires essentially no external test stimulus other than a “start test” control signal and avoids breaking the DLL feedback loop. Simulations of a prototype DLL show 95% overall structural-fault coverage, while also providing some ability to detect degraded static phase error, jitter, lock range, and lock time. 

What Problem the Paper Addresses

DLLs are widely used for high-precision clock generation, clock deskewing, clock recovery, interchip communication, and clock-distribution systems. At high data rates, even relatively small clock/data misalignment can cause system failures.

Testing embedded DLLs is difficult for several reasons:

• DLLs may have little or no direct connection to primary chip inputs or outputs.
• Failure of a system-level timing specification does not automatically identify the DLL as the faulty component.
• DLL faults can create intermittent timing failures and logic errors through excessive jitter or incorrect phase alignment.
• Many earlier PLL/DLL test methods require opening the control loop or inserting multiplexers into sensitive timing paths.
• Added test circuitry can introduce delay offsets or load sensitive analog nodes, potentially degrading normal performance.

The paper therefore targets a lower-overhead objective than precision on-chip timing measurement: identify faulty DLLs during manufacturing without significantly modifying or disturbing the DLL itself.

Questions the Paper Answers

The paper investigates several practical test questions:

1. Can an embedded DLL be tested without opening its feedback loop?
2. Can phase-lock failure be detected using only simple digital circuitry?
3. How can the BIST tolerate normal DLL static phase error and jitter while still detecting faulty behavior?
4. Can uncalibrated delay elements provide adequate timing resolution?
5. What proportion of catastrophic structural faults can the proposed method detect?
6. Which structural faults remain undetected?
7. Can the same technique detect performance degradation caused by parametric variations?
8. How does repeating the test affect fault detection, false failures, and total test time?

Key Technical Terms and Definitions

Delay-Locked Loop (DLL):
A feedback timing circuit that adjusts a voltage-controlled delay line until its output clock is phase-aligned with the input reference clock.

Voltage-Controlled Delay Line (VCDL):
A chain of delay stages whose propagation delay is controlled by a voltage. In the studied DLL, the total VCDL delay is driven toward one reference-clock period.

Phase Detector (PD):
A circuit that determines the phase difference between the DLL reference clock and the delayed output clock.

Charge Pump (CP):
A circuit that converts phase-detector information into charging or discharging current for the DLL loop filter.

Static Phase Error:
The residual time difference between the reference clock and DLL output clock after the DLL has locked.

Jitter:
Short-term variation in clock timing. The paper specifically evaluates cycle-to-cycle jitter.

Built-In Self-Test (BIST):
Test circuitry incorporated into an integrated circuit so that internal functionality can be checked with little external test equipment.

Structural Fault:
A physical circuit defect such as an open connection or an unintended short.

Parametric Fault:
A manufacturing-related variation that does not necessarily create a complete electrical open or short but causes circuit performance to move outside acceptable limits.

Fault Detection Resolution:
The minimum phase difference between the reference and output clock that causes the BIST to report a failure.

XNOR Gate:
A digital logic gate whose output is high when its two inputs have the same logical value. In this BIST, it acts as a simple phase-comparison element.

Workflow

The circuit architecture is illustrated particularly clearly in the diagrams on page 3. The DLL reference clock and final VCDL output are fed to an XNOR gate, while an inverter-chain-based sampling-clock generator provides two observation points around the relevant reference-clock transition. 

The test proceeds as follows:

1. Compare the clocks.
   The DLL reference clock and output clock are applied to an XNOR gate.
2. Observe phase-error glitches.
   A perfectly aligned pair of clocks would ideally keep the XNOR output high. Real DLLs produce short glitches because of static phase error and jitter.
3. Sample on both sides of the reference-clock transition.
   The XNOR output is sampled twice:
   • once to detect excessive lag of the DLL output;
   • once to detect excessive lead.
4. Generate sampling times with an uncalibrated delay chain.
   Instead of using precision calibrated delay circuitry, the design uses inverter stages whose delay varies with process, voltage, and temperature.
5. Combine the samples.
   An AND operation produces the test decision. If both observations indicate acceptable phase alignment, the DLL passes.
6. Delay testing until lock should have occurred.
   The test is enabled through a “start test” signal after sufficient time has elapsed for a fault-free DLL to lock.
7. Optionally repeat the test.
   Multiple test cycles can be combined using a register and AND logic, as shown in the paper’s page-6 implementation, improving detection of intermittent or non-locking behavior.
8. Scan out the digital result.
   The stable pass/fail output can be read through an IEEE 1149.1 boundary-scan path or another available scan mechanism. 

Main Findings

High Structural-Fault Coverage

The authors simulated 473 structural faults across the phase detector/charge pump, loop filter, and VCDL.

Table I on page 7 reports the following coverage:

Fault Type	Fault Coverage
Gate open	71%
Source open	100%
Drain open	100%
Gate-drain short	100%
Gate-source short	100%
Drain-source short	100%
Capacitor short	100%
Overall	95%

By functional block, Table II reports:

DLL Block	Fault Coverage
Phase detector + charge pump	100%
Loop filter	100%
VCDL	93%

All of the undetected structural faults occur in the VCDL. 

Structural Faults Produce Observable Timing Signatures

According to Table III, detected faults predominantly produce one of two types of behavior:

• 59% cause a substantial phase lead/lag or cause the DLL to fail to lock.
• 41% cause the DLL output clock to become stuck at logic 0 or logic 1.

These behaviors are well matched to the proposed XNOR-based detection strategy. 

Resolution Is Determined by the DLL’s Normal Timing Variation

For the prototype DLL, the authors report static phase-error values over process, voltage, and temperature of approximately:

• minimum: 60 ps
• typical: 80 ps
• maximum: 110 ps

Cycle-to-cycle jitter ranges from 13.6 ps to 58.1 ps, with a typical value of 25.2 ps.

The selected target detection resolutions were approximately:

• 240 ps when the DLL output lags the reference;
• 60 ps when the DLL output leads the reference.

These unequal limits reflect the statistical behavior of the prototype rather than a requirement that phase-error detection be symmetrical. 

Repeated Tests Improve Detection but Increase False-Reject Risk

The multiple-test architecture shown on page 6 stores successive results and requires every test to pass.

This reduces the likelihood that a faulty, unlocked DLL is accidentally classified as good. However, Figure 10 also shows the corresponding tradeoff: increasing the number of tests raises both test time and the probability that an otherwise good circuit is rejected because of timing variation.

For the structural-fault problem studied in the paper, the authors identify two test cycles as a useful balance between detecting lock failures and avoiding excessive false failures. 

Some Parametric Performance Degradation Can Be Detected

The BIST is not primarily a precision parametric measurement instrument, but the simulations indicate useful sensitivity to degraded DLL behavior.

For static phase error, a single test provides a 95% detection probability at approximately:

• 82 ps when the output leads the reference for typical devices;
• 89 ps for the corresponding slow-device case;
• 279 ps when the output lags for typical devices;
• 288 ps for slow devices.

With five tests, the corresponding approximate thresholds improve to:

• 61 ps and 59 ps for leading error;
• 256 ps and 258 ps for lagging error.

The benefit eventually saturates because detection is fundamentally limited by the chosen BIST timing resolutions. 

Large Jitter Increases Can Also Be Detected

For cycle-to-cycle jitter, the paper reports approximately 95% detection probability for jitter exceeding:

• 345 ps for typical devices with one test;
• 358 ps for slow devices with one test;
• 162 ps for typical devices with five tests;
• 170 ps for slow devices with five tests.

The authors therefore suggest that large jitter degradation caused, for example, by substrate or power-supply noise may be detectable with the technique. 

Technical Significance

The main technical contribution is not extreme measurement resolution. Instead, it is the ability to obtain a useful DLL health indication with very limited intrusion into the circuit under test.

Several characteristics distinguish the design:

• The DLL feedback loop remains closed.
• No multiplexer is inserted into the phase-detector path.
• Sensitive loop-filter nodes do not need to be externally driven.
• The primary measurement element is a simple XNOR gate.
• Sampling delays do not require calibration.
• The output is a conventional digital pass/fail signal.
• No external analog stimulus is required.

This shifts DLL testing from precision measurement toward efficient defect screening.

The result is particularly relevant to design-for-test situations where the cost and invasiveness of the test circuitry are as important as measurement accuracy.

Industrial Impact

For semiconductor manufacturing, the proposed method could support wafer-level screening of embedded timing circuits before defective parts incur additional packaging and test costs.

Potential industrial advantages include:

• earlier identification of defective DLLs;
• better localization of timing-related yield problems;
• low BIST area overhead;
• compatibility with boundary-scan infrastructure;
• reduced dependence on expensive external analog timing measurement;
• minimal disruption of high-performance analog/mixed-signal nodes;
• scalability to chips containing multiple DLL-based clock domains.

The authors explicitly frame the approach as useful for obtaining efficient fabrication feedback during wafer sort and preventing clearly faulty DLL-containing circuits from proceeding to packaging. 

Why the Paper Matters

The paper illustrates an important mixed-signal test-design principle: a manufacturing test does not always need to measure every specification accurately to be valuable.

Instead of building complex circuitry to measure jitter, phase error, and lock characteristics precisely, the proposed BIST converts several different failure mechanisms into a much simpler question about phase alignment.

That simplification makes it possible to achieve strong structural-fault coverage with modest hardware.

The work also demonstrates how test resolution must be designed around the statistical behavior of the good circuit. Jitter and normal static phase error place a lower bound on how aggressively the BIST can distinguish faulty devices without creating excessive false rejects.

Limitations and Scope

Several limitations are stated or demonstrated in the paper.

Structural coverage is not complete.
Overall coverage is 95%, with several VCDL gate-open faults escaping detection. Some of these faults can still allow the DLL to lock because remaining delay stages compensate for the defective stage.

Internal stage matching is not directly tested.
A DLL may reach global phase lock while individual VCDL stages have uneven delays. The proposed BIST compares only overall input-to-output phase behavior.

Duty-cycle performance is not evaluated.
The authors explicitly note that duty cycle and inter-stage delay matching are outside the performance characteristics considered.

Parametric faults are only partially detected.
The circuit is not a complete jitter or phase-error measurement system. Its ability to detect parametric degradation depends on fault magnitude, test resolution, operating corner, and number of tests.

The sampling delay chain is uncalibrated.
This greatly reduces implementation complexity but makes the effective detection threshold dependent on process variation.

Technology scaling introduces uncertainty.
The authors expect the method to scale toward faster DLLs, but they identify increased device variability in advanced processes as a potential limitation. The uncalibrated delay chain may eventually require modifications or larger devices to reduce timing uncertainty. 

Concise Technical Abstract

Jia and Milor present a low-overhead BIST architecture for fault detection in embedded delay-locked loops. The method applies the DLL reference and output clocks to an XNOR gate and samples the resulting phase-error glitches at two points generated by an uncalibrated inverter delay chain. The approach preserves the DLL feedback loop, avoids inserting multiplexers into sensitive timing paths, and requires no external stimulus other than test control. Simulations using a 0.18-µm prototype DLL evaluate 473 catastrophic structural faults and report 95% overall coverage, including 100% coverage in the phase detector/charge pump and loop filter and 93% in the VCDL. The circuit also provides limited detection of excessive static phase error, jitter, lock time, and lock-range degradation. Its main design tradeoff is between test resolution, rejection of good circuits, and detection of faulty ones, with normal DLL jitter ultimately limiting achievable sensitivity.