A DLL Design for Testing I/O Setup and Hold Times

Full citation: Cheng Jia and Linda Milor, “A DLL Design for Testing I/O Setup and Hold Times,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 17, no. 11, pp. 1579–1592, November 2009. DOI: 10.1109/TVLSI.2008.2005522. A_DLL_Design_for_Testing_I_O_Se…

Plain-Language Overview

High-speed memory interfaces depend on extremely precise timing between incoming data and the clock used to capture that data. Two fundamental constraints are the setup time—how long data must be valid before the clock edge—and the hold time—how long it must remain valid afterward.

Jia and Milor propose an on-chip built-in self-test (BIST) circuit that tests these two timing requirements independently. Instead of requiring an expensive external tester capable of picosecond-level edge placement, the chip itself generates carefully shifted clocks using a delay-locked loop (DLL). The external equipment primarily supplies the reference clock.

The important idea is that a relatively low-resolution, eight-stage DLL can still support accurate timing tests. Rather than relying solely on extremely fine physical delay steps, the design adjusts the test frequency, repeats measurements over multiple cycles, and compensates for systematic phase error. The fabricated prototype demonstrates a measured DLL lock range of 150–400 MHz. With averaging and compensation, the authors report delay-generation errors below approximately 40 ps for the targeted timing range. A_DLL_Design_for_Testing_I_O_Se…

What Problem the Paper Addresses

Traditional setup- and hold-time testing requires an external tester to position data and clock edges with very high accuracy. When the timing specification itself is only a few hundred picoseconds, tester edge-placement uncertainty can become a substantial fraction of the quantity being measured.

The problem becomes particularly important at wafer probe, where loading introduced by the test environment can further degrade timing accuracy.

Earlier I/O loopback BIST techniques reduce dependence on external testers, but they generally evaluate an input and output path together. Consequently, they do not directly verify the separate setup- and hold-time specifications appearing in device datasheets, and paired-path testing can permit fault masking. The authors therefore target an on-chip method that tests setup and hold requirements separately. A_DLL_Design_for_Testing_I_O_Se…

Questions the Paper Answers

The paper investigates several closely connected questions:

• Can setup and hold times of high-speed I/O registers be tested independently using on-chip circuitry?
• Can a comparatively simple, low-resolution DLL provide sufficient timing accuracy without a phase interpolator?
• How can changing the DLL reference frequency generate delays corresponding to different timing specifications?
• How do process, supply-voltage, and temperature variations affect DLL jitter, static phase error, lock range, and lock time?
• Can repeated test cycles reduce uncertainty caused by jitter?
• Can compensation for static phase error further improve timing accuracy?
• What accuracy-versus-test-time tradeoff results from these techniques?

The work addresses these questions through circuit design, simulation across PVT conditions, fabrication in a 0.18-µm CMOS process, and measurements from prototype devices.

Key Technical Terms and Definitions

Setup time: The minimum interval for which input data must already be valid before the active clock edge.

Hold time: The minimum interval for which input data must remain valid after the active clock edge.

Built-In Self-Test (BIST): Hardware incorporated into an integrated circuit so that the device can generate and/or evaluate its own test conditions with reduced dependence on external test equipment.

Delay-Locked Loop (DLL): A feedback circuit that adjusts a chain of delay elements until the total delay through the chain corresponds to one period of the reference clock. Intermediate stages provide phase-shifted versions of that clock.

Voltage-Controlled Delay Line (VCDL): The adjustable delay chain inside the DLL. Its stage delays are controlled by an analog voltage.

Phase Detector (PD): Circuitry that detects the phase difference between the reference clock and the delayed feedback signal.

Charge Pump (CP): Circuitry that converts phase-error information into charging or discharging current for the DLL loop filter.

Static phase error: The residual phase difference between the reference clock and the final DLL output after the loop has locked.

Jitter: Short-term variation in clock-edge timing. The paper primarily evaluates cycle-to-cycle jitter.

PVT variations: Variations in semiconductor process, supply voltage, and temperature, all of which can change circuit timing.

Shift averaging: A VCDL arrangement used to improve matching between individual delay stages and improve the duty cycle of the generated clocks.

Lock range: The range of input clock frequencies over which the DLL can successfully establish delay lock.

Lock time: The amount of time required for the DLL to reach its locked condition.

Workflow

The architecture shown in Figures 3–5 on page 3 combines a data generator, tristate buffers, two additional test registers, a DLL-based setup/hold clock generator, and comparison circuitry. A_DLL_Design_for_Testing_I_O_Se…

The testing procedure can be summarized as follows:

1. Generate test data on chip. The BIST data generator supplies the I/O being tested. Other I/Os can receive random patterns to produce power-grid noise and ground bounce representative of operating conditions.
2. Generate timing-shifted clocks. An eight-stage analog DLL creates multiple delayed versions of the clock.
3. Select setup and hold clock phases. The required DLL stages provide clocks positioned relative to the normal core clock according to the timing specification being tested.
4. Adjust the reference frequency. Because each DLL stage represents a fraction of one clock period, changing frequency changes the absolute delay represented by that stage. This allows one eight-stage DLL to address several timing specifications.
5. Capture the data in three registers. The normal input register and two nearby test registers capture the signal using the normal, setup-test, and hold-test clocks.
6. Compare captured values. A three-input XNOR-based comparison determines whether all three registers captured the same value.
7. Repeat the measurement when higher accuracy is required. Multiple test cycles are performed and the number of passes is evaluated. Majority-based averaging reduces sensitivity to random jitter.
8. Compensate for static phase error. The test frequency can additionally be modified to account for systematic DLL phase error.

This workflow deliberately tests whether the interface satisfies specification boundaries rather than attempting to reconstruct the entire data-valid window.

Main Findings

The prototype was fabricated using a TSMC 0.18-µm CMOS process. The measured DLL operated over a 150–400 MHz lock range. Measurements from seven prototype chips showed that jitter generally improved as operating frequency increased. Measured static phase error was approximately 65–90 ps, averaging about 85 ps, while measured lock time was only one to four cycles, or roughly 5–12 ns. A_DLL_Design_for_Testing_I_O_Se…

The measurements also demonstrate why simply generating one delayed clock is insufficient for high-accuracy testing. For a nominal 500-ps target, the measured distributions showed setup-clock delays of approximately 358–472 ps and hold-clock delays of approximately 527–642 ps at the 5%–95% probability points. Across the considered specifications, uncompensated delay-error bounds could approach 200 ps. A_DLL_Design_for_Testing_I_O_Se…

The authors therefore apply two accuracy-improvement techniques.

First, multiple-cycle testing reduces sensitivity to jitter. Instead of making the pass/fail decision from one clock event, many trials are performed and their results combined statistically.

Second, static-phase-error compensation changes the test frequency to compensate for systematic DLL timing offset.

Combining 100 test cycles with static-phase-error compensation reduces the calculated delay-error bounds to below 20 ps when the static phase error of the particular DLL is known. However, because static phase error itself varies with PVT conditions, using an average compensation value gives a more conservative worst-case bound of approximately 40 ps. The authors suggest calibration of individual DLLs as a route to still lower errors. A_DLL_Design_for_Testing_I_O_Se…

Technical Significance

A central contribution of this work is demonstrating that high timing-test accuracy does not necessarily require extremely fine intrinsic DLL phase resolution.

A conventional approach could use more delay stages or a phase interpolator to create very small physical timing increments. Jia and Milor instead exploit the mathematical relationship between DLL stage delay and clock period. Changing the reference frequency changes the absolute time represented by each stage.

This shifts part of the problem from hardware resolution into test methodology. Frequency adjustment provides the desired nominal delay, repeated measurements suppress the influence of random jitter, and phase-error compensation addresses systematic timing offset.

The design also addresses practical DLL requirements created by this strategy. Because testing requires several frequencies, the DLL needs a broad lock range. Because frequencies may change during production testing, fast locking reduces test overhead. The architecture therefore incorporates a start-control mechanism and modified phase-detector/charge-pump behavior intended to avoid false locking and accelerate acquisition. A_DLL_Design_for_Testing_I_O_Se…

Industrial Impact

The approach is relevant to production testing of high-speed memory and parallel I/O interfaces because it moves precision timing generation onto the device being tested.

That can potentially reduce dependence on expensive automatic test equipment with extremely fine timing-edge placement. It is particularly relevant to wafer-level testing, where external loading makes accurate I/O timing characterization more difficult.

The architecture is also partially shareable across multiple I/Os: the DLL and data-generation resources can serve several channels, while test registers and comparison circuitry remain associated with individual I/Os. This creates an implementation tradeoff between silicon overhead, DLL loading, and the realism of simultaneously generated switching noise. A_DLL_Design_for_Testing_I_O_Se…

The industrial implication is therefore not simply “put a DLL on the chip.” The paper presents a test architecture in which modest-resolution on-chip timing hardware is combined with frequency control and statistical testing to obtain substantially finer effective measurement accuracy.

Why the Paper Matters

The paper addresses the growing mismatch between increasingly tight I/O timing specifications and the cost and accuracy limitations of external production-test equipment.

Its broader contribution is methodological: measurement resolution can be improved algorithmically and statistically rather than entirely through more complex timing hardware.

The work also separates setup and hold testing instead of relying exclusively on loopback measurements that combine input and output path behavior. That makes the resulting test more directly aligned with the individual timing specifications manufacturers publish for digital interfaces. A_DLL_Design_for_Testing_I_O_Se…

For test engineers and mixed-signal/VLSI designers, the paper provides an example of co-design between circuit architecture and test strategy: DLL architecture, operating frequency, jitter, PVT sensitivity, number of test cycles, calibration, silicon area, and total test time all contribute to the achievable measurement accuracy.

Limitations and Scope

The proposed technique has several important constraints.

The fabricated DLL’s measured 150–400 MHz lock range was narrower than simulations predicted. The authors note that other DLL techniques could be used to extend this range. A_DLL_Design_for_Testing_I_O_Se…

Accuracy also depends strongly on jitter and static phase error. The simulations intentionally do not fully represent all environmental jitter sources, such as reference-clock noise, power-supply switching noise, and ground bounce, so simulated jitter represents a lower bound under the assumptions used in the paper.

There is an additional test-time versus accuracy tradeoff. Performing 100 or more test cycles improves statistical confidence but necessarily lengthens testing.

The strongest reported accuracy from combined averaging and phase-error compensation assumes knowledge of the DLL’s static phase error. Because that quantity varies with PVT conditions, practical implementation either accepts the roughly 40-ps worst-case bound associated with average compensation or introduces a calibration procedure. A_DLL_Design_for_Testing_I_O_Se…

Physical implementation also introduces scaling constraints. Routing one DLL’s phase signals to very large numbers of I/Os increases loading and can degrade timing accuracy. Data generators and pad-driving tristate circuitry introduce area overhead, while sharing them among channels can make generated switching noise less representative of actual operation. A_DLL_Design_for_Testing_I_O_Se…

Finally, the work specifically focuses on setup and hold testing for high-speed memory-interface I/Os. The authors indicate that the general approach can be extended to other interface timing specifications, but those extensions are not experimentally demonstrated in this paper.

Concise Technical Abstract

Jia and Milor present a built-in self-test architecture for independently verifying setup and hold timing specifications of high-speed I/O interfaces. The design uses an eight-stage analog DLL to generate phase-shifted test clocks and varies the reference frequency to obtain different absolute delay values without requiring a high-resolution phase interpolator. On-chip data generation, test registers, and comparison logic allow timing verification with minimal external tester functionality beyond reference-clock generation. The fabricated 0.18-µm CMOS prototype demonstrates a measured DLL lock range of 150–400 MHz, static phase error averaging approximately 85 ps, and lock times of 1–4 cycles. Single-cycle measurements remain sensitive to jitter and systematic phase error, but multiple-cycle averaging substantially reduces random uncertainty. Combining 100-cycle averaging with static-phase-error compensation produces calculated error bounds below 20 ps when device-specific phase error is known; accounting for PVT-dependent phase-error variation yields an approximately 40-ps worst-case bound using average compensation. The work demonstrates how frequency adjustment, statistical averaging, and calibration can convert a comparatively low-resolution DLL into an accurate on-chip timing-test resource for high-speed memory interfaces. A_DLL_Design_for_Testing_I_O_Se…