Determining the Impact of Within-Die Variation on Circuit Timing

Full citation: Muhammad Muqarrab Bashir and Linda Milor, “Determining the Impact of Within-Die Variation on Circuit Timing,” IEEE Transactions on Semiconductor Manufacturing, vol. 24, no. 3, pp. 385–391, Aug. 2011. DOI: 10.1109/TSM.2011.2152865.

Plain-Language Overview

Integrated circuits made with the same manufacturing process do not behave identically. Even within a single chip, transistor dimensions and electrical properties vary from place to place. These within-die variations can change which signal path is the slowest—or “critical”—and therefore complicate timing closure.

Bashir and Milor develop a way to analyze this problem without exhaustively simulating every possible combination of manufacturing variations. Their key idea is to separate within-die variation into systematic and random components. Systematic variation is compressed using principal components analysis (PCA), producing a finite set of representative manufacturing “corners.” Circuit timing can then be evaluated at those corners. Random variation is handled statistically.

The paper’s central result is that, under the authors’ linear timing model and a ±3σ PCA variation domain, the worst systematic timing behavior occurs at one of these corners. This converts what would otherwise be a large continuous search problem into a finite set of timing analyses.

What Problem the Paper Addresses

Traditional variability analysis often combines die-to-die and within-die process variation when estimating circuit performance. The authors argue that within-die variation deserves separate treatment because different devices and paths on the same chip can experience different process conditions. As a result, within-die variation can reorder critical paths rather than merely shifting the timing of the entire die in the same direction.

The practical problem is computational complexity. Systematic manufacturing variation can depend on transistor location, nearby geometry, pattern density, lithography conditions, and other spatial effects. Explicitly considering every combination would be prohibitively expensive.

The authors therefore seek a compact set of process conditions that still captures the important timing extremes associated specifically with within-die variation.

Questions the Paper Answers

The study addresses whether systematic within-die variation can be represented by a finite set of process corners, whether those corners are sufficient to expose critical timing paths, and how neighborhood-dependent and location-dependent variations should be modeled.

It also examines whether the remaining random variations in transistor critical dimension and threshold voltage show significant short-range spatial correlation after systematic patterns have been removed.

Finally, the paper asks whether systematic and random within-die effects can be separated in a way that enables a practical statistical static timing analysis methodology.

Key Technical Terms and Definitions

Within-die variation refers to differences in device or interconnect parameters at different positions within the same integrated-circuit die.

Die-to-die variation represents shifts that differ between dies but affect devices within an individual die more globally.

Critical dimension (CD) in this paper primarily refers to the transistor gate dimension whose variation affects transistor current and circuit delay.

Threshold voltage (Vth) is the MOSFET gate voltage associated with the onset of significant channel conduction. Variation in Vth changes transistor speed and therefore timing.

Systematic variation is variation related to repeatable process or layout effects. Examples discussed by the authors include lithographic proximity effects, lens aberrations, flare, etching effects, pattern density, neighborhood geometry, and position within a die.

Random variation refers to device-to-device fluctuations that remain after systematic trends have been removed, including effects associated with random dopant fluctuations and line-edge roughness.

Principal components analysis (PCA) is a dimensionality-reduction technique that transforms correlated variables into new orthogonal axes called principal components. The paper uses these axes to describe dominant systematic variation patterns.

Systematic corner is an extreme combination of principal-component values. The authors define their domain using ±3 standard deviations for the retained principal components; combinations of those extremes create the corners to be evaluated.

Statistical static timing analysis (SSTA) applies statistical models of parameter variation to circuit timing rather than evaluating only a single deterministic timing condition.

Workflow

The methodology can be summarized as follows:

Collect manufacturing data. Neighborhood- and location-dependent CD information is obtained from test structures distributed across the reticle, while closely spaced transistor-array measurements are used for random-variation analysis.
Separate systematic effects. When a small data set simultaneously contains location, neighborhood, and density effects, contributions unrelated to the effect being studied are subtracted before further analysis.
Apply PCA to systematic variation. Principal components are extracted from the covariance structure of the CD data.
Define a ±3σ principal-component domain. Extreme combinations of the retained principal components define a finite set of systematic corners.
Map the corners back to physical CD values. Each PCA corner becomes a pattern of transistor CDs associated with neighborhood or spatial position.
Perform circuit timing analysis at the corners. Because the assumed delay expression is linear in CD variation and the PCA domain is convex, the maximum of that expression occurs at a corner.
Check for nonlinear effects. In the multiplier example, the authors also simulate conditions on faces of the PCA cube to determine whether additional critical paths appear.
Remove systematic trends from transistor-array measurements. Residual CD and Vth variations are then tested for spatial correlation.
Model the residual random component statistically. Because little adjacent-device correlation remains in the examined data, the authors model random variation using effectively independent random variables and propose statistical timing analysis at each systematic corner.

Main Findings

For neighborhood-dependent systematic variation, PCA greatly reduces the number of conditions that need to be investigated. In one manufacturing data set, three principal components captured the variation, yielding eight PCA corners. Four corners were associated primarily with dense/isolated linewidth bias, while four represented coma-like lithographic variation.

The approach was tested on a 64-bit pipelined multiplier with 45,453 gates, 45,584 nets, six pipeline stages, a 400 μm × 400 μm area, and a target frequency of 667 MHz. The circuit contained 20 critical paths. Under nominal conditions, path 6 was the critical path. Across the eight systematic neighborhood corners, paths 5 and 15 also became critical under some conditions, although path 6 remained the longest path at the worst neighborhood corner. The circuit diagram and timing comparison appear on page 4 of the paper.

The authors also tested six additional conditions on faces of the PCA cube. No additional critical paths were detected in this experiment, supporting—but not universally proving—the usefulness of corner-based analysis when the timing response is sufficiently close to linear.

For location-dependent variation, the study likewise found that relatively few principal components represented most of the observed spatial structure. In the synthetic cross-wafer example, two significant principal components explained 99.5% of the variation. For manufacturing data analyzed across both large and smaller die regions, four principal components accounted for more than 90% of the variation, producing 16 systematic corners.

The random-variation analysis produced another important result. Once the systematic spatial trend was removed, adjacent-device CD correlation was below 0.01 in the examined data, based on a correlation sample size of 1,896. Residual threshold-voltage variation likewise showed adjacent-site correlation below 0.02.

The regression analysis further found that approximately 7.5% of the measured threshold-voltage variability was explained by variation in CD. The raw and modeled CD and Vth patterns are illustrated on page 6 of the paper.

Technical Significance

The paper provides a mathematical justification for reducing systematic within-die timing analysis to a corner-evaluation problem.

If circuit delay is modeled as a linear function of CD variation, and systematic variation is restricted to a convex multidimensional domain bounded by the retained PCA components, then a linear objective reaches its maximum at a vertex of that domain. Consequently, the search for a worst-case critical path does not require sampling the entire continuous process-variation space; evaluating the finite set of PCA corners is sufficient under those assumptions.

This is important because the PCA coordinates are not arbitrary independent worst cases. They are extracted from observed covariance in process data. The resulting corners therefore reflect correlated manufacturing behavior more realistically than simply assigning independent ±3σ extremes to every physical variable.

The proposed decomposition can be summarized conceptually as

device CD = nominal CD + neighborhood systematic variation + location systematic variation + random CD variation.

Threshold-voltage variation is then modeled with a CD-dependent component plus a residual random component.

This separation creates a natural interface between deterministic corner analysis for layout-dependent systematic variation and statistical timing analysis for residual random variation.

Industrial Impact

For semiconductor manufacturing and timing signoff, the methodology suggests a route to incorporating measured process variability without requiring unrestricted Monte Carlo exploration of every systematic spatial pattern.

A fabrication line could derive PCA-based systematic corners from test-structure measurements. Those corners could then be incorporated into cell characterization or circuit timing analysis so that design teams evaluate process patterns that are actually supported by manufacturing data.

The approach is also relevant to timing closure because within-die variation can cause a path that is noncritical at nominal conditions to become critical after fabrication. The multiplier experiment directly demonstrates this effect: additional paths became timing-critical at particular systematic corners.

Another practical implication concerns modeling complexity. Once systematic spatial patterns were removed from the authors’ transistor-array data, the residual CD and Vth fluctuations exhibited negligible short-range correlation. For those data sets, the random component therefore did not require a complicated layout-dependent spatial correlation model.

These industrial implications should be interpreted within the technologies and measurements studied rather than assumed to hold unchanged for modern processes.

Why the Paper Matters

The paper connects manufacturing measurements, statistical dimensionality reduction, physical variation modeling, and circuit timing analysis in a single framework.

Its most useful conceptual contribution is the distinction between two fundamentally different problems. Layout-dependent systematic variability is represented through experimentally derived process corners, while irreducible random variability is addressed statistically at those corners.

This avoids treating every source of process variation in the same way. It also explains why conventional single “worst-case” timing assumptions can be incomplete: different within-die variation patterns can change the identity and physical location of the critical path.

Although semiconductor processes have advanced substantially since the paper was published in 2011, the underlying problem—efficiently connecting spatial process variability to circuit-level timing risk—remains central to variation-aware design.

Limitations and Scope

The authors explicitly restrict the investigation to minimum-sized transistors, noting that circuit speed is particularly sensitive to transistor variability. Interconnect variability is therefore not analyzed with the same level of detail.

The systematic CD example uses data from an older 0.18 μm technology, which the authors present as an illustration of the methodology rather than as a representation of a current process. The random-variation transistor-array measurements come from a 65 nm technology.

The theoretical corner result depends on modeling delay as a linear function of CD variation over the region of interest. The paper acknowledges that if circuit delay becomes strongly nonlinear, evaluating only the corners may fail to expose every possible critical path. The additional face simulations in the multiplier experiment provide an empirical check for that particular example rather than a general proof for arbitrary circuits.

The PCA corner count can also become large. With n retained principal components, the corner construction can produce up to 2^n combinations. The authors note that if many systematic components are needed, the required simulation effort could approach that of Monte Carlo analysis. They therefore identify efficient exploration of large systematic-corner spaces as an area for future work.

Finally, the findings of negligible residual spatial correlation apply to the examined data after systematic components were removed. The paper does not establish that random CD or Vth variation will always be spatially independent for every manufacturing technology or process generation.

Concise Technical Abstract

Bashir and Milor present a methodology for isolating and evaluating the effect of within-die transistor variation on circuit timing. Within-die variation is decomposed into systematic neighborhood- and location-dependent components and residual random variation. Principal components analysis is used to identify dominant systematic CD variation modes and construct a finite set of ±3σ process corners. Under a linear delay model over the resulting convex PCA domain, worst-case timing occurs at a corner, allowing critical paths associated with systematic variation to be identified through a finite number of circuit simulations. Application to a 64-bit pipelined multiplier demonstrates that systematic variation can reveal critical paths that differ from the nominal critical path. Analysis of a 65 nm transistor array additionally shows negligible short-range spatial correlation in residual CD and threshold-voltage variation after systematic patterns are removed. The paper therefore proposes combining systematic-corner simulation with statistical timing analysis of random device variation.